以低溫共燒陶瓷製程設計和模型化抑制兆赫茲同步切換雜訊的微小化寬能隙結構

為了達到寬頻的兆赫茲雜訊抑制效果，一個可當元件使用的新式寬能隙結構被提出。此結構由三維的交疊式電容與U型傳輸線週期性串接而成並利用低溫共燒陶瓷製程的特性達到縮小化的效果。為了快速預測截止頻帶，理論的模型也將被建立。此模型能成功的描述出該縮小化結構在高頻時內部的電感性耦合效應。藉由全波模擬軟體的使用與量測，模型的精確性可以得到驗證。同時，利用此模型的協助，不同的結構參數與截止頻帶的關係也將一併被探討。在此論文中，實作成品大小為1.2mm×3.8mm×0.728mm ，模擬與量測結果相當吻合。截止頻帶範圍約為2~5.5 GHz，在此範圍內，雜訊至少有25 dB的抑制效果。除此之外，我們也從事此結構與晶片封裝系統的共模擬，從實驗結果可以發現，在數位與類比電路中，都有很好的雜訊抑制能力。

關鍵字

寬能隙結構；同步切換雜訊；低溫共燒陶瓷製程

並列摘要

A novel electromagnetic band gap (EBG) structure as a component is proposed for broadband suppression of GHz simultaneous switching noise. The structure is composed of three-dimensional interdigital capacitors (3D-IDC) and series U-shaped transmission lines periodically. The EBG structure can be miniaturized based on the LTCC fabrication technology. A theoretical circuit model which considers the inductive coupling in the 3D-IDC will be developed to predict the stop band. The accuracy of the proposed model will be verified by comparing with both the full-wave simulation and the measurement results. This modeling method is also employed to study the variation of band gap dependent on different geometrical parameters for the 3D-IDC and the U-shaped transmission line. A prototype is implemented using the LTCC technology with the dimension 1.2mm×3.8mm×0.728mm. Both simulation and measurement show the rejection band is from 2GHz to 5.5GHz. Over 25dB noise reduction in the stop band could be achieved. In addition, the suppressive ability is also verified in the chip-package co-simulation. From the simulation result, significant reduction of power noise could be found both in digital and mixed signal circuits.

並列關鍵字

EBG ； SSN ； LTCC

參考文獻

[1] International Technology Roadmap for Semiconductors.

[2] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits, vol. 26, pp. 1724-1728, Nov. 1991.

[3] S. V. den Berghe, F. Olyslager, D. de Zutter, J. d. Moerloose, and W. Temmerman, “Study of the ground bounce caused by power plane resonances,” IEEE Trans. Electromag. Compat., vol. 40, pp. 111-119, May 1998.

[4] T. L. Wu, Y. H. Lin, J. N. Hwang, and J. J. Lin, “The effect of test system impedance on measurements of ground bounce in printed circuit boards,” IEEE Trans. Electromag.Compat., vol. 43, pp. 600-607, Nov. 2001.

[5] K. Ren, C. Y. Wu, and L. C. Zhang, “The restriction on delta-I noise along the power/ground layer in the high-speed digital printed circuit board,” in Proc. IEEE Int. Symp. Electromag. Compat., Colorado, USA, Aug. 1998, pp. 511-516.

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以低溫共燒陶瓷製程設計和模型化抑制兆赫茲同步切換雜訊的微小化寬能隙結構

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