注入脈波寬度校正與三角積分時間轉換數位器的低雜訊應用鎖相迴路

Low Noise Application of Phase-Locked Loops with Injection-Pulse-Width Calibration and Delta-Sigma Time-to-Digital Converters

魏志旅(Chih-Lu Wei)

指導教授 ： 劉深淵

共同指導教授 ： 汪重光

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10586

摘要

這篇論文的主題主要分為兩個部分，第一部分我們實現了一個次諧波注入鎖相迴路搭配一個脈波寬校正迴路。我們使用了次諧波注入之技巧去壓抑震盪器之相位雜訊。此外，我們提出了一個注入脈波寬度校正之技巧去探討注入脈波寬對於相位雜訊的影響。量測到的相位雜訊在適當的脈波寬度下可以達到較佳的雜訊效能。此外，量測環境在溫度0~80 oC、電壓1.02~1.18V下，適當的脈波寬度也能使方均根抖動獲得改善。
第二部分實現了一個數位鎖相迴路搭配了一個三角積分時間轉換數位器。我們使用了過度取樣的技巧去改善數位鎖相迴路頻寬內的量化雜訊，並且在震盪器控制的控制路徑上使用了前饋調控的架構降低了迴路延遲，因此改善了相位雜訊效能。此外，簡化的一階三角積分調變器架構也可以降低時間轉換數位器的功耗和面積。量測到的方均根抖動為861fs，我們提出的三角積分時間轉換數位器的功耗、面積分別為0.519 mW、0.0027mm2。

關鍵字

時脈產生器

並列摘要

This thesis consists of two parts. The first part implement a subharmonically injection-locked PLL with a pulse-width-calibrated loop. Subharmonically injection-locked technique is employed to suppress VCO accumulation noise. Besides, we propose an injection-pulse-width calibration technique to discuss the pulse width of injected pulse for the impact on the phase noise. The measure phase noise can achieve better noise performance by the proper pulse width of injected pulse. Moreover, the measured environment at temperature 0~80oC 、supply voltage 1.02~1.18V, the RMS jitter performance also can be improved by the proper pulse width of injected pulse.
The second part implements a Digital PLL with a delta-sigma time-to-digital converter (ΔΣ TDC). We use the oversampling technique to improve the in-band quantization noise of DPLL, and use the feedforward tuning architecture in the controlled path of the digitally-controlled oscillator to reduce the loop latency. Therefore, the phase noise performance is improved. Additionally, the simple first-order delta-sigma modulator architecture also reduce the power and area of TDC. The measured RMS jitter is 861fs. The power consumption and active area of the proposed ΔΣ TDC are 0.519 mW、0.0027mm2 respectively.

並列關鍵字

Clock Generators

參考文獻

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