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  • 學位論文

適用於熱感知三維晶片網路之資源分配與可適性路由演算法

Resource Allocation and Adaptive Routing Algorithm for Thermal-Aware Three-Dimensional Network-on-Chip

指導教授 : 吳安宇

摘要


本篇論文針對三維晶片網路之熱感知設計的效能降低做出改善。我們分別提出兩種設計技巧:1) 針對過熱關閉元件之三維晶片網路下的可適性路由演算法 2) 針對流量遷移的資源分配演算法。為了促進三維晶片網路之熱感知設計與相關研究,我們亦提出模擬平台:3) 針對三維晶片網路的流量-溫度共同模擬平台。對於過熱關閉造成的流量阻塞,我們提出一可適性路由演算法以改善網路效能。此可適性路由演算法基於奇偶路由法,能感知網路上的流量資訊以及過熱關閉資訊,進而自動選擇適當路徑,使封包能繞開過熱關閉元件以及平衡網路負載。由於能降低三維晶片網路的穩態溫度的流量遷移,帶來各層不平衡的網路負載並造成流量阻塞。我們針對流量遷移提出一資源分配演算法,藉由分配不同層上路由器上的緩衝器深度,平衡各層的網路負載,進而改善網路效能。因為現行模擬平台缺乏支援流量與溫度的共同模擬,我們自行開發一模擬平台,以支援上述兩種熱感知設計與相關效能改進技術。此模擬平台亦經由商用溫度模型工具驗證其垂直面的熱傳導模擬,以確保相對性上的正確度。

並列摘要


In this thesis, we proposed two techniques to improve the performance degradation of thermal-aware 3D NoC designs: 1) Adaptive routing for throttled 3D NoC. 2) Resource allocation for traffic migration. And we also proposed: 3) a traffic-thermal co-simulation platform for 3D NoC to facilitate the two kinds of thermal-aware design. To address the traffic congestion due to throttling of transient-temperature control, we proposed an adaptive routing algorithm. Based on the Odd-Even routing function, a traffic- and throttling-aware selection strategy is proposed to decide proper routing path to balance network traffic and detour throttled tiles. While the traffic congestion happens after the traffic migration of steady-temperature optimization, we proposed a design flow of resource allocation. Depend on the loading requirement at each layer, our allocation assigns suitable buffer depth for each layer under a constraint of total buffer cost. Our proposed simulation platform supports unidirectional coupling and mutual coupling. And we validate the proposed simulation platform with commercial thermal modeling tool, CFD-RC, to assure the relative correctness of vertical heat conduction.

參考文獻


[1] ITRS, International Technology Roadmap for Semiconductors, [Online]. Available: http://public.itrs.net.
[4] D. Sylvester and K. Keutzer, “A global wiring paradigm for deep submicron design,” IEEE Trans. CAD/ICAS, vol. 19, pp. 242-252, Feb. 2000.
[5] L. Benini and G. De Micheli, “Networks on chips: A new SoC paradigm,” IEEE Computer, vol. 35, pp. 70–78, Jan. 2002.
[6] A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini and M. Ieong, “Three-dimensional integrated circuits,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491-506, 2006.
[7] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen and C. Webb, “Die stacking (3D) microarchitecture,” in Proc. Int. Symp. Microarchitecture, pp. 469-479, Dec. 2006.

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