本論文研究可在平行多電子束直寫系統上作為電子束源的矽針陣列之製作。為了產生高的場發射電流,尖銳的矽針陣列是必要的。本論文不使用傳統熱氧化削尖方式,而是在研究不同方法的可行性後提出直接使用反應式離子蝕刻系統完成矽針削尖。這個方法是重覆執行乾蝕刻流程直到二氧化矽遮罩掉落為止。每次乾蝕刻時間設定間隔將不會超過一分鐘以避免矽針過蝕刻情形發生。基本上,矽針陣列形成過程仍是以乾蝕刻為主,但另一種結合氫氧化鉀濕蝕刻和乾蝕刻的方法則可減少乾蝕刻所需時間。矽針之間設計的間隔約在40~100微米之間。實驗結果顯示此種結合方法的確可有效地減少乾蝕刻所需時間,同時完成的矽針半徑可達30奈米或以下,而且對於矽針的高度也有所幫助。為了減少場發射電流的起始電壓,我們也製作閘極場發射陣列。我們提出的方法較為簡單與可靠並可在同一流程中完成矽針與金屬閘極。矽針陣列的電流電壓曲線符合Fowler-Nordheim理論。同時從單一矽針與4×4矽針陣列量測到的電流大小分別為數個與數百毫微安,此量測到的電流值已比高晶圓產量所需的電流值高。
This dissertation discusses the fabrication of sharp n-type silicon tip arrays for the e-beam source to be used in a massively parallel direct-write electron-beam system. The sharp silicon tip array is essential to produce high emission current. The fabrication procedure used in this dissertation does not require the conventional thermal oxidation sharpening process. Instead, this study looks into various possibilities and proposes a new sharpening process using only controlled reactive-ion etching (RIB) system. This process is then performed repeatedly until the mask falls. The interval of RIE etching time is kept under 1 min to avoid over-etching of the silicon tips. Basically, the underlining tip-formation process is still based on dry-plasma etching, but a combination of dry etching and wet KOH etching reduces the time required for dry-etching. The designed distance between adjacent tips is 40 ~ 100 um. Our experimental results show that such combination does effectively reduce the dry-etching time. It is also observed that the tip radius achieved is about 30 nm or less, and the tip height can be increased. To reduce threshold voltage, we also fabricate gated field emission array. Our proposed method is simple and reliable, and it can produce the sharp silicon tip and metal gate in the same procedure. The field emission experiments are carried out to measure the performance of our vacuum device. The I-V characteristic of our field emission array agrees with Fowler-Nordheim theory. The measured emission current is several nano-ampere from one single tip and several hundreds of nano-ampere from a 4×4 tip array. This current is higher than the required current for high wafer etching throughput (10 wafers/hour) requirement.