數位訊號處理器系統層級功率評估

System-level Power Estimation for Digital Signal Processor

吳新傳(Xin-Chuan Wu)

指導教授 ： 楊佳玲

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.01377

摘要

在本論文中，我們提出一個指令層級功率估測(Instruction-level power estimation)方法來估算當軟體在嵌入式超長指令字(VLIW)數位訊號處理器(digital signal processor)的耗電量。指令層級功率估測被廣泛運用於軟體優化，其速度比電路層級與邏輯閘層級模擬快數個數量級，而估測誤差率約在10-20%。這份研究顯示將此方法應用於嵌入式超長指令字數位訊號處理器，模擬時間可由數十分鐘縮短至數秒鐘，而誤差約在4-14%。為了估測目標數位訊號處理器執行一程式時的耗電量，我們將目標數位訊號處理器分為三個主要的部分，分別為數位訊號處理器核心，資料記憶體，以及其他耗電量固定的元件。針對數位訊號處理器核心，根據其硬體使用方法，可將之分為共享硬體資源以及獨立硬體資源，而我們分別詳細的描述其耗電情形。針對資料記憶體，兩個主要因素會影響其耗電量：(1) 讀寫動作的次數 (2) 每一次讀寫動作的耗電量。我們提出一個指令層級功率評估方式適用於超長指令字數位訊號處理器，這是考慮記憶體存取以及可變長度指令技術的評估方法。在我們的實驗中，我們所提出的方法降低誤差使得估測最大誤差在4%以內，而額外的模擬負擔為可忽略的。

關鍵字

指令層級功率估測 ； 超長指令字 ； 數位訊號處理器

並列摘要

In this thesis, we present an improved instruction-level power estimation tool to evaluate the power consumption associated with a software code for an embedded VLIW digital signal processor (DSP). Instruction-level power estimation is widely used in software optimizations, of which the speed is order of magnitude faster than circuit- and gate-level simulations and the estimation error is within 10-20%. This work presents its application on an embedded VLIW DSP. The simulation time is reduced from tens of minutes for a kernel-level task to only few seconds and the estimation error is about 4-14%. To estimate the power consumption of target DSP running a program, we partition a target DSP into three major parts, DSP core, data memory and other components that have fixed power consumption. For DSP core, based on the usage of the hardware resources, it can be separated into shared hardware resources and isolated hardware resources, and we model the power consumption respectively. For data memory, we observe two major factors to affect the power consumption of data memory: (1) the number of read/write operation. (2) the power consumption of each read/write operation. We propose an improved power model for instruction-level power estimation of VLIW DSP, which takes into account the memory accesses and the variable-length instructions that are common in such architectures. In our experiments, the proposed approach reduces the maximum estimation error to only 4% and the simulation overheads are neglectable.

並列關鍵字

Instruction-level power estimation ； VLIW ； digital signal processor

參考文獻

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