基於標準CMOS製程並具T型多晶矽光柵之崩潰式光感二極體

本研究以聯華電子 (UMC) 所提供之 0.18 μm 1 poly 6 metal (1P6M) 標準CMOS製程於無使用後製程下設計、製作並量測一具二維T型多晶矽光柵結構之崩潰式光感二極體。根據數值分析結果，當以850 nm 之平面波入射具光柵結構之數值模型其17 μm 厚之矽基底吸收率較無光柵結構之數值模型提高了約36.8979 %。藉由計算T型光柵結構之繞射效率空間分布並結合繞射角與繞射次序 (diffractive order) 之關係可解析入射光與光柵間之繞射行為，並因Ｔ型光柵短邊結構之些微影響使元件具低繞射依賴度之特性。由有限元素法（Finite Element Method）之模擬結果發現電洞之游離係數隨逆向偏壓增加之增幅較電子來得大，原因為電洞於矽材料中欲達累崩式碰撞電離之門檻能量較電子來得高，最後將游離係數比率與不同文獻矽材料之實驗結果相比可驗證計算結果具一定的準確度。在數值模型之效能分析上考量光電子、電洞於矽基底之生成率、摻雜布局、逆向偏壓及量子效率等特性，由結果得本研究所設計之光柵結構可提升32.4269 % 之光電流效能。在實驗量測方面，以851.537 nm 具160.1 μW 之任意偏振雷射光入射本研究所設計之光感二極體，由發生累崩式碰撞電離前之平均光電流量測結果得T型多晶矽光柵結構於實際量測上可提升元件29.8891 %之效能。當以具415.6 nW任意偏振入射具光柵結構之元件得最大有效響應度為3961 (A/W)對應之累崩因子 (multiplication factor)為2.385×10⁴而無光柵結構之元件其最大有效響應度為3571 (A/W)對應之累崩因子為2.151×10⁴。最後，藉由調變入射光之偏振態並得響應度之標準差為0.11907，進而推論本研究所設計之具T型光柵結構之崩潰式光感二極體與設計目標相符為偏振依賴度極低之元件。

關鍵字

累崩式光感二極體；標準CMOS製程； T型多晶矽光柵；游離係數；繞射效率

並列摘要

Avalanche photodiodes (APDs) with and without a T-shaped poly-Si grating in 0.18-μm 1 poly 6 metal (1P6M) standard CMOS technology are presented. The numerical results show that the absorptance in a multilayered PD structure with a 17-μm -thick Si-substrate of in the presence of sub-optimal T-shaped poly-Si grating is 36.8979 % higher than that without a grating. The diffraction characteristics of the T-shaped poly-Si grating are further investigated in terms of the diffraction efficiency, angles of diffraction, and diffracted order. A two-dimensional poly-Si grating with finite-length strips is shown to be polarization insensitive. The short stub in the T-shaped structure has little impact in the optical performance. On the other hand, finite-element-based simulation show that, since the threshold ionization energy of holes is higher than that of electrons in silicon, the increase in the ionization coefficient of holes is faster than electron’s as the reverse bias is increased. Considering the spatial distribution of generation rate in the silicon substrate, doping profiles, and the quantum efficiency. Simulated photocurrent from the model with sub-optimal T-shaped poly-Si grating is 32.4269 % higher than the one without grating. The measured average unamplified photocurrent and the responsivity of the APD with a T-shaped poly-Si grating are 29.8891 % higher than the one without grating under light incidence at 851.537 nm and 160.1 μW. The maximum responsivity reaches 3961 (3571 A/W) and the corresponding multiplication factor is 2.385×10⁴ (2.151×10⁴) for the APD with (without) grating, respectively, at a reverse bias of 15.55 (15.5) V, when illuminated with light of 415.6 nW. The standard deviation of the measured responsivity from the APD with grating is 0.11907 for the polarization angle from 0^∘ to 90^∘, which fairly verifies the grating design.

並列關鍵字

Avalanche Photodiode ； Standard CMOS Process ； T-shaped poly-Si grating ； ionization coefficient ； diffraction efficiency

參考文獻

[1] Y. Miyamoto, M. Yoneyama, K. Hagimoto, T. Ishibashi, and N. Shimizu, “40 Gbit/s high sensitivity optical receiver with uni-travelling-carrier photodiode acting as decision IC driver,” IEEE Elctron. Lett., vol. 34, no. 2, pp. 214-215, Jan. 1998.

[2] D. Huber, R. Bauknecht, C. Bergamaschi, M. Bitter, A. Huber, T. Morf, A. Neiger, M.Rohner, I. Schnyder, V.Schwarz, and H. Jäckel,“InP-InGaAs single HBT technology for photoreceiver OEIC‘s at 40 Gb/s and Beyond,” J. Lightw. Technol., vol. 18, no.7, pp. 992-1000, Jul. 2000.

[3] L. D. Garrett, J. Qi, C. L. Schow, and J. C. Campbell, “A silicon-based integrated NMOS-p-i-n photoreceiver,” IEEE Trans. Electron. Devices, vol. 43, no. 3, pp. 411-416, Mar. 1996.

[6] B. Ciftcioglu, L. Zhang, J. Zhang, J. R. Marciante, J. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard 0.18-um CMOS technology,” Phys. Rev., vol. 27, no. 15, pp. 3303-3313, Aug. 2009.

[7] W. K. Huang, Y. C. Liu, and Y. M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,”IEEE Photon.Technol. Lett., vol. 19, no. 4,pp. 197-199, Feb. 2007.

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基於標準CMOS製程並具T型多晶矽光柵之崩潰式光感二極體

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