標準CMOS高壓技術製作之單光子累崩二極體

在本論文中，我們探討藉由台積電0.18 μm高壓製程製作的單光子累崩二極體(SPADs)。我們設計且製作了不同PN接面的SPAD，並分析它們的特性，元件在設計時的模擬以及後續的分析是透過Sentaurus-TCAD軟體進行。在製作的元件中，特性最好的元件是直徑20 μm，由Deep P-well(DPW)與N-type Buried Layer(NBL)形成PN接面的SPAD。與先前實驗室製作的元件相比，該元件不僅有低暗計數(DCR)、高光子響應率(PDE)、低時基誤差(jitter)，還有較低的崩潰電壓。我們重新模擬元件結構，藉由調整後的濃度分佈，來討論與解釋DPW/NBL元件特性較好的原因。然而，在jitter與入射波長的關係中，我們在波長720 nm附近觀察到了不尋常的趨勢，我們將在未來作進一步的探討。

關鍵字

單光子；高壓；單光子累崩二極體；單光子偵測

並列摘要

In this work, we investigate single-photon avalanche diodes (SPADs) in standard 0.18-m high-voltage CMOS technology provided by TSMC. The SPADs with various kinds of P-N junctions have been designed, fabricated, and characterized. Device simulation and afterward analysis are performed with Sentaurus-TCAD tool. Among the studied devices, 20-m-diameter SPADs formed with deep p-typed well (DPW) and n-typed buried layer (NBL) have the best performance including low dark count rate (DCR), high photon detection efficiency (PDE), low jitter and reduced breakdown voltage comparing with the previous ones in our group. Possible reasons for the improvement are discussed and explained by the simulation on revised doping profiles of the layers. However, the dependence of jitter on the photon wavelength exhibits unusual behavior around 720 nm and calls for further studies in the future.

並列關鍵字

single photon avalanche diode ； SPAD ； high voltage ； single photon

參考文獻

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[2] D. Stoppa, D. Mosconi, L. Pancheri, and L. Gonzo, “Single-photon avalanched diode CMOS sensor for time-resolved fluorescence measurements,” IEEE Sensors J., vol. 9, no. 9, pp. 1084–1090, Sep. 2009.

[3] C. Niclass, M. Soga, H. Matsubara, S. Kato, and M. Kagami, “A 100-m range 10-frame/s 340 96-Pixel time-of-flight depth sensor in 0.18 μm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 559–572, Feb. 2013.

[4] Y. Yamashita, H. Takahashi, S. Kikuchi, K. Ota, M. Fujita, S. Hirayama, T. Kanou, S. Hashimoto, G. Momma, S. Inoue,“A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitry”, IEEE Int. Solid State Circuit Conf., pp.408-410 , 2011.

[5] E. Kamrani, F. Lesage, M. Sawan, “Towards on-chip integration of brain imaging photodetecors using standard CMOS process,” 35th Annual International Conference of the IEEE EMBS, July, 2013

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標準CMOS高壓技術製作之單光子累崩二極體

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