使用CMOS製作之高速類比通訊積體電路設計

The Design of High-Speed Analog Communication IC in CMOS

王懷德(Huai-De Wang)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2010年)

https://doi.org/10.6342/NTU.2010.10072

摘要

受惠於製程技術的進步，互補式金氧半導體(CMOS)元件的截止頻率已經超過100 GHz，由於其具有功率消耗小，容易與數位電路整合等特性，使得在CMOS製程上實現通訊前端類比電路成為一個相當有競爭力以及吸引力的方式。在另一方面，隨著通訊產業的發展，人們互相交流的資訊量也日益增加，對於通訊電路的需求也越來越大，也越來越要求低成本以及低功耗。故本論文將以使用CMOS製程製作之高速類比通訊電路為主題，討論包含應用於有線通訊以及高頻無線通訊的電路設計。在有線通訊方面，我們將討論我們在高速背版通訊收發機、改善鎖相迴路雜訊，以及高速介面電路等三方面的研究。而在高頻無線通訊電路方面，我們將呈現我們在60-GHz 無線收發機的晶片設計以及模組整合的成果。
在第二章中，我們首先將對背版通訊收發機作一研究分析。隨著操作頻率的提升，通道衰減所造成的影響也日益嚴重，我們將對常用的前饋式等化器，以及決策回饋式等化器的能力作一探討，討論在不同係數數量下，對於等化器所帶來的影響。而後，我們也對全速以及半速架構在傳送端以及接收端下的優缺點進行分析討論。在瞭解等化器的特性後，我們設計了一個半速傳送機以及全速的接收機，利用先進CMOS製程的優點，設法大量使用數位化電路，降低電感的使用量，並配合提出的新式決策回饋式等化器，來達到降低功率消耗，提升傳輸距離等目的。此電路利用65-nm CMOS製程設計製作，在僅87 mW的功率消耗下，可以21-Gb/s的速度在40-cm FR4 通道的傳輸距離。
緊接著，我們對於次諧波注入鎖定式鎖相迴路進行討論研究。雖然注入鎖定技巧已被大量使用在壓震盪器以及除法器的頻率鎖定上，但是其與鎖相迴路的結合使用卻鮮為人知，而過往的文獻也缺乏完整的理論分析驗證。也因此，我們在此主題中，分析研究了次諧波注入鎖定的情形，並利用實體晶片做完整的理論測試，而後利用此技術，實作了兩個鎖相迴路，大幅改善鎖相迴路雜訊，達到目前所知最低雜訊的高速(20-GHz附近)的鎖相迴路。在第四章中，我們也將此技術整合至一40-Gb/s的發送機。40-Gb/s 為以太網路適用的頻率，過往大多使用III-V族製程。在此電路中，我們採用半速架構，來解決CMOS頻寬不足的問題，同時配合多樣的頻寬增強技巧，降低功率消耗。而採用的次諧波注入鎖定式鎖相迴路，可提供一乾淨的半速時脈，大幅降低輸出的資料抖動。此晶片使用90-nm CMOS製程製作，可提供4:1的多工器功能，在1.5 V電壓下消耗325 mW，達到454 fs,rms 輸出資料抖動，為目前CMOS發表的最低資料抖動。
論文最後討論到無線60-GHz收發機的技術，作為下一代室內高速資料或影音傳輸的規格，我們期望製作出低功率，低成本的收發機模組。在此研究中，我們不僅將前端電路完全整合，也利用類比式的頻率鍵移調變技術來收發資料來達到降低電路功率以及電路複雜度的目的，其中在解調器部分，我們提出一自動頻率追蹤的方法，可有效提升解調器的靈敏度。配合使用電路印刷版製作的天線，以及覆晶封裝技術，完整製作了60-GHz的收發模組。此60-GHz 的頻率鍵移調變收發機在1 Gb/s的資料傳輸量下，傳輸距離可達1公尺。

關鍵字

背版通訊 ； 等化器 ； 注入鎖定 ； 鎖相迴路 ； 60-GHz ； 頻率鍵移調變 ； 收發機

並列摘要

Along with the improvement of process, the cutoff frequency of CMOS devices has exceeded 100 GHz. Because CMOS features its low power and high integration, it is very attractive to implement analog front-end circuit for communication in CMOS. The development of the communication industry also encourages people exchange information. The increasing demand of high-speed communication drives us to study on the CMOS design for low-cost and low-power communication. This thesis will discuss about our research results of the circuit design for high-speed communication in CMOS. In wireline communication, we focus on high-speed backplane transceiver, improving phase noise of the PLL, and high-speed I/O circuits. On the other hand, we are also devoted to developing 60-GHz wireless transceiver design and the module integration.
In chapter 2, we will give an analysis on the backplane transceiver. With the increasing of operation frequency, the channel loss becomes more serious, and thus equalizers have been widely adopted in transceiver design. As a result, we will discuss the limitation of FFE and DFE at first, addressing the effect of the tap number of the equalizers. After that, the benefits of full-rate and half-rate architectures in transmitter and receiver will be described in detail as well. Understanding the properties of the equalizers, we present a half-rate transmitter and full-rate receiver. With the advance CMOS process, we use digital circuit as much as possible to reduce the requirement of the inductance. Incorporating with novel DFE, the power consumption can be reduced significantly but the communication distance can be increased. Designed in 65-nm CMOS, the transceiver can deliver 21-Gb/s data over 40-cm FR4 channel with 87 mW.
Following that, we will talk about the subharmonically injection-locking PLL design. Although injection locking technique has been widely used in VCO and divider, only few works have present the combination of injection locking with PLL. To fully understand the subharmonically injection locking, we gives a complete analysis and theory verification in silicon in this chapter. We also apply this powerful technique to two 20-GHz PLLs, achieving the lowest phase-noise high-frequency (around 20 GHz) PLL. In the chapter 4, we also apply this technique to a 40-Gb/s transmitter. To achieve bandwidth requirement, we adopt half-rate structure in this design. Triple-peaking technique is also applied to speed up the circuit operation. With a subharmonically injection-locking CMU, the output data jitter has been reduced as well as power has been saved. Designed and fabricated in 90-nm CMOS technology, this chip provides 4:1 multiplexing and achieves 454 fs,rms output data jitter while consuming only 325 mW from a 1.5-V supply.
Finally, we will present the design of 60-GHz transceiver for wireless communication. As an indoor high-speed data or video communication standard, we are looking for a low-power and low-cost transceiver solution. In this topic, not only integrating the front-end circuit, we also adopt analog FSK modem to achieve data communication, which saves considerable power by reducing circuit complexity. A background frequency-tracking topology is also proposed to improve the sensitivity of the FSK demodulator. With the on-board folded-dipole antenna, we arrive at a fully-integrated 60-GHz module with flip-chip technique. The transceiver can deliver 1 Gb/s data over 1 m.

並列關鍵字

backplane communication ； equalizer ； injection locking ； phase-locked loop (PLL) ； 60-GHz ； FSK ； transceiver

參考文獻

[1] D-L. Chen and M. Baker, “A 1.25Gb/s, 460mW CMOS Transceiver for Serial Data Comunication,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 242-243, Feb. 1997.

[2] C-K. Yang et al., “A 0.6μm CMOS 4Gb/s Transceiver with Data Recovery using Oversampling,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 71-72, June 1997.

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[4] R. Farjad-Rad et al., “A 0.3-μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 41-44, June 1999.

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