適用於鎖相頻率合成器之突波雜訊抑制技術研究

A Spur Suppression Technique for Phase-Locked Frequency Synthesizers

李韋良(Wei-Liang Lee)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00821

摘要

隨著無限通訊系統的快速發展，對於具有高精確度，低功率消耗與快速鎖定時間鎖相迴路的需求也隨著顯著增加。在設計鎖相迴路時，常常需要在鎖定時間的長短與輸出端參考側帶的強度大小之間作取捨，這個情形限制了鎖相迴路的電路表現，同時也降低了在設計鎖相頻率合成器時的自由度。

在這篇論文中，我們介紹了一個適用於整除數頻率合成器的離散式相位頻率偵測器/充電泵浦架構，在不改變系統迴路參數的情形下，可以有效的降低突波雜訊的強度。為了要抑制此架構中所使用開迴路延遲線的非理想效應，更進一步的採用脈衝位置調變的方法來調變控制電壓上的波動位置，將突波雜訊的的能量分散開來，使參考側帶的強度更加降低。

一個操作在4.8-GHz，具有四組離散式相位頻率偵測器/充電泵浦與脈衝位置調變機制的鎖相頻率合成器在台積電零點一八微米互補金氧半製程環境下設計並且製作完成。晶片的面積大小為一毫米乘於零點九毫米。經過實際量測的結果顯示，與傳統的鎖相頻率合成器相較，此架構可以降低突波的強度達10 dB，在使用一點八伏特供應電壓的情形下電流消耗為十毫安陪。在距離2.4-GHz輸出1-MHz處的相位雜訊為-110 dBc/Hz。

關鍵字

鎖相迴路 ； 頻率合成器 ； 脈衝位置調變

並列摘要

With the rapid growing of the wireless communication system, the demands of high precision, low power and fast settling time phase-locked loops (PLLs) increase significantly. The design of PLL generally deals with a tight tradeoff between the settling time and the magnitude of the reference sidebands that appears at the PLL output. This tradeoff limits the performance and leaves very little freedom to design a phase-locked frequency synthesizer.

In this thesis, we introduce an architecture with distributed phase frequency detectors (PFDs) /charge pumps (CPs) for integer-N frequency synthesizer to reduce the magnitude of the reference spur significantly without changing the loop parameters. To suppress the nonidealities of the open-loop delay lines used in the proposed architecture, pulse-position modulation (PPM) technique is adopted to modulate the positions of ripples on the control line and spread the spur power, decreasing the magnitude of the reference sideband further.

A 4.8-GHz phase-locked frequency synthesizer with four distributed PFDs/CPs and PPM is designed and fabricated in TSMC 0.18-μm CMOS technology. The chip size is 1 mm × 0.9 mm. The experimental result shows that the proposed architecture can reduce the spur magnitude by 10 dB, compared with the conventional architecture, while dissipating only 10 mA from a 1.8-V power supply. The phase noise of the 2.4-GHz output is -110 dBc/Hz at 1-MHz offset.

並列關鍵字

PLL ； frequency synthesizer ； PPM

參考文獻

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