應用於手提式數位電視接收器之 具邊頻改善頻率合成器

A Spur-Reduction Frequency Synthesizer for DVB-H Receivers

陳信樺(Hsin-Hua Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00204

摘要

固定式或可攜式接收地面數位電視訊號的系統---又稱作數位電視地面廣播 (DVB-T)---已經被使用了好幾年。在下一階段的發展，數位電視使用在手提式裝置以及整合全球行動通訊系統 (GSM) 是無法避免的趨勢。為了要能支援這些新的應用，一種新的標準稱作手提式數位電視 (DVB-H)，已經變成一個熱門的焦點。
在射頻系統裡，頻率合成器的設計仍然是最富挑戰性的議題之一。因為它必須要達到非常嚴苛的要求，例如：穩定時間 (settling time)、相位雜訊、參考餽入 (reference feedthrough)---又被稱作參考邊頻 (reference spur)，…等。在設計頻率合成器時，有幾個權衡取捨 (trade-off) 會出現。首先，穩定時間長短主要取決於迴路頻寬 (loop bandwidth) 大小。同時因為考量迴路的穩定性，迴路頻寬會被限制在大約1/10的參考頻率。接著，壓控震盪器的相位雜訊只有在小於迴路頻寬時才會被回授的迴路所減低。最後，我們需要縮小迴路頻寬來降低參考邊頻。為了解決這些權衡取捨，我們已經設計出幾種新的架構，採取電荷守恆 (charge conservation) 以及取樣與保持 (sample-and-hold) 的概念來達到一個快速鎖定、寬頻帶以及低參考邊頻的鎖相迴路 (phase-locked loop)。
在論文裡，第二章會介紹鎖相迴路的的基本理論以及頻率合成器的重要特性。之後會描述如何設計一個頻率合成器的設計流程，並且運用一些例子來做行為模擬 (behavior simulation) 上的驗證。
第三章將會介紹我們提出的頻率合成器架構，此作品是使用0.18微米互補式金氧半導體混合信號製程來實現。一開始我們會先探討我們的動機，包含幾個設計上的重點，例如：相位雜訊、切換時間 (switching time)、參考邊頻…等。接下來，電路的分析以及實現將被詳細的介紹。最後，我們會呈現這個作品的實驗結果。
第四章提出三種新架構以進一步降低參考邊頻。藉由這些新架構，之前使用的架構所存在的兩個主要缺點可以被大幅的改善。同樣的，我們在這一章結束前會呈現實驗結果。
第五章是我們對這個論文所做的結論，同時會與其他已經發表的論文做比較。一些值得未來繼續研究的項目也會被提出加以討論。

關鍵字

頻率合成器 ； 鎖相迴路 ； 數位電視

並列摘要

The system for fixed and portable reception of digital terrestrial television, known as digital video broadcasting-terrestrial (DVB-T), has been available for several years. Making this available for handheld devices is the next step, along with integration into global system for mobile communications (GSM) is an inevitable trend. In order to support these new applications, a new standard called digital video broadcasting-handheld (DVB-H) has become a popular topic.
Synthesizer design still remains one of the most challenging issues in RF systems because it must meet very stringent requirements such as: settling time, phase noise, reference feedthrough (also called reference spur), etc. Several trade-offs exist in the design of synthesizer. First, the settling time is largely determined by the loop bandwidth which is limited to approximately 1/10 of the reference frequency for loop stability considerations. Second, the phase noise of the oscillator is reduced by the feedback loop only within the loop bandwidth. Finally, in order to suppress the reference spur, a small loop bandwidth is required. To solve all these trade-offs, we have proposed several new architectures adopting the charge conservation and sample-and-hold concepts to achieve a fast locking, wide range, and low reference spur PLL.
Chapter 2 will give basic ideas of phase-locked loops (PLLs) as well as some important characteristics in a frequency synthesizer. A design flow is described along with detailed parameter setting and architecture simulations together with some examples are demonstrated.
Chapter 3 will present our proposed frequency synthesizer which is fabricated in 0.18-um CMOS process. At first, we will discuss the motivation including several design issues, such as: phase noise, switching time, reference spur… Then, analysis and implementation of our circuit are introduced in detail. Finally, we will present the experimental results of this work.
In chapter 4, three new architectures will be proposed to further improve the spur-reduction function. Two main drawbacks of the structure proposed in chapter 3 can be improved greatly. Also, the experimental results will be presented in the end of this chapter.
Finally, chapter 5 will give some conclusions to this work, comparing and contrasting the architectures presented in this paper with other published works. Issues that should be noted for future work on this topic are also discussed.

並列關鍵字

frequency synthesizer ； PLL ； DVB-H

參考文獻

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