具次諧波相位自動對準技術之無除頻器次諧波注入頻率合成器

A Dividerless Subharmonically Injection Locked Frequency Synthesizer with Self Injected Signal Aligning

吳培鈞(Pei-Chun Wu)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10711

摘要

本地振盪器(local oscillator)在無線通訊系統中，扮演著很重要的角色。在射頻收發機中，通常是使用鎖相迴路系統作為本地振盪器。類比鎖相迴路至今已有相當長的發展歷史，在許多方面也已發展得趨於成熟，但許多特性仍有加以改進的空間，例如: 鎖定時間(settling time)、相位雜訊(phase noise)、參考突波(reference spur)等。其中相位雜訊的改善依舊是一個相當具有挑戰性的議題，針對此議題，也不斷地發展出新的技術加以改善。
近幾年針對相位雜訊改善發展出了許多新的技術，其中無除頻器之頻率合成器與次諧波注入鎖相迴路為兩種改善較為顯著的技術，然而這兩種技術中，仍有許多發展尚未完善之處，例如: 鎖相迴路中不同模式的切換、次諧波注入的相位對準等。現有的技術中，普遍使用手調的方式來進行切換與相位對準，為了改善此點，本論文提出了一個新型的架構，在能自動切換不同鎖定模式的同時，也能在次諧波注入時自動進行相位對準。

關鍵字

鎖相迴路 ； 相位雜訊 ； 無除頻器頻率合成器 ； 次諧波注入 ； 相位對準

並列摘要

Local oscillator plays an important role in wireless communication system. In radio frequency transceivers, phase locked loops are frequently used as a local oscillator. The development of analog phase-locked loop has a long history, and it has certainly become very well developed. However, there are still plenty of requirements that need to be improved upon, such as settling time, phase noise, reference spur, etc. Among these requirements, phase noise is still a challenging issue. Since then, many new techniques have been developed in order to improve the phase noise performance.
Several new techniques have been created in recent years, two of which are worth noting here: dividerless phase locked loop and subharmonically injection locked phase locked loop. Both have seen great improvements in phase noise performance. However, there are still parts of the systems that are not well developed, such as switching between different modes, phase alignment of subharmonically injection locked PLL, etc. Nowadays people manual switch between modes and manually adjust for phase alignment. This paper proposes a new architecture which not only self-switches between different modes but also does the self-alignment for subharmonically injection locked PLL.

並列關鍵字

Phase Locked Loop ； Phase Noise ； Dividerless Frequency Synthesizer ； Subharmonically Injection Locked ； Self-alignment

參考文獻

[1] X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A low noise subsampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,” IEEE J. Solid-State Circuits, vol. 44, pp. 3253-3263, Dec. 2009.

[2] X. Gao, et al., “A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18μm CMOS,” IEEE Int. Solid-State Circuits Conf. Tech. Dig, Feb. 2009, pp. 392-393.

[3] X. Gao, E. Klumperink, G. Socci, M. Bohsali and B. Nauta, “Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector,” IEEE J Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sep. 2010.

[4] A. Shahani, et al., “Low-power dividerless frequency synthesis using aperture phase detector”, IEEE J.Solid-State Circuits, vol. 33, pp. 2232-2239, Dec. 1998.

[5] D. Cai et al., “A 2.1-GHz PLL with -80dBc/ -74dBc reference spur based on aperture-phase detector and phase-to-analog converter,” Proc. IEEE ASSCC Symp. Dig., Nov. 2011, pp. 141-144.