針對乙太網路系統設計之功能性分析及驗證

Functional Analysis and Verification of Ethernet System Design

蔡松達(Sung-Ta Tsai)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202201495

摘要

乙太網路標準迅速發展以滿足高速傳輸之需求，導致其實作的複雜度不斷增加，而實作過程中難免出現功能性的錯誤。本論文提出了一種功能性驗證方法，用於驗證乙太網路設計中功能之正確性，在 RTL 階段找出實作上的錯誤，進一步減少在物理設計階段不必要的成本及損失。我們使用 SystemVerilog 實作測試平台中的匯流排功能性模組來模擬乙太網路的資料連結層和實體層之行為，也在其中插入斷言以表示乙太網路標準中定義之錯誤行為並用於評估覆蓋率，此外我們設計測試方法以檢查匯流排功能性模組中實作功能之正確性，並可用於驗證乙太網路的設計是否正確。 我們在匯流排功能性模組中插入了 40 個斷言並設計了 83 個測試方法， 並進行模擬來驗證測試平台的功能實作是否正確，而實驗結果顯示所有測試方法皆通過模擬，且所有斷言皆被觸發，代表我們的驗證方法達成 100% 覆蓋率，也說明我們的測試平台運作正確，可用於驗證乙太網路的設計。我們也針對 2.5GBASE-T 以及 100G-KP4 乙太網路的位元錯誤率進行比較，以便分析乙太網路之錯誤更正能力。驗證新的乙太網路標準可基於既有的測試平台進行實作，節省時間並有效率的達成功能性驗證之目的。

關鍵字

乙太網路 ； 功能性驗證 ； 匯流排功能性模組 ； 斷言 ； 覆蓋率 ； 位元錯誤率

並列摘要

Ethernet standard has evolved rapidly to fulfill the needs of high speed transmission, which causes the complexity of Ethernet design increases constantly. It’s inevitable to have functional errors during design implementation. A functional verification methodology is presented to verify the correctness of functions in Ethernet design, find design errors in RTL and reduce unnecessary cost in physical design. We construct testbench that contains Bus Functional Model (BFM) to simulate the behavior of Ethernet data link layer and physical layer by SystemVerilog. Assertions are added in BFM to represent invalid behavior and used to evaluate coverage. Testcases are developed to verify both our testbench and Ethernet design. Experiments on 83 testcases all pass simulation and 40 assertions in our BFM are all triggered, which proves our testbench achieves 100% coverage and works properly to verify Ethernet design. To analyze error correction capability, we also compare Bit Error Rate (BER) performance of 2.5GBASE-T and 100G-KP4 Ethernet. Verifying new speed types of Ethernet can reuse the existing testbench, which reduces the time of implementation for new standards and efficiently achieves the goal of functional verification.

並列關鍵字

Ethernet ； Functional Verification ； Bus Functional Model ； Assertion ； Coverage ； Bit Error Rate

參考文獻

[1] P. Hank, S. Muller, O. Vermesan, and J. Van Den Keybus, “Automotive ethernet: ¨ in-vehicle networking and smart mobility,” in 2013 Design, Automation Test in Europe Conference Exhibition (DATE). IEEE, 2013, pp. 1735–1739.

[2] X. Zhao, V. Vusirikala, B. Koley, V. Kamalov, and T. Hofmeister, “The prospect of inter-data-center optical networks,” IEEE Communications Magazine, vol. 51, no. 9, pp. 32–38, 2013.

[3] “IEEE Standard for Ethernet,” IEEE Std 802.3-2018 (Revision of IEEE Std 802.3- 2015), pp. 1–5600, 2018.

[4] “IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language,” IEEE STD 1800-2009, pp. 1–1285, 2009.

[5] H. Zimmermann, “OSI reference model-the ISO model of architecture for open systems interconnection,” IEEE Transactions on communications, vol. 28, no. 4, pp. 425–432, 1980.