具漏流補償和快速鎖定之鎖相迴路

隨著CMOS製程的快速進步，對於高速的通訊系統的需求也逐漸增加。而其中扮演一個很重要的角色就是時脈產生器，時脈產生器往往決定了系統的速度以及效能，然後在先進製程90nm或65nm製程中，漏電流的問題會嚴重地影響時脈產生器的效能，本論文的目的在解決時脈產生器在深次微米製程下所遇到的問題；最後一部份會提出達到快速鎖定效能的鎖相迴路。鎖相迴路和延遲鎖定迴路被廣泛地應用在時脈產生器。而鎖相迴路通常適用於高速應用，因此也常用動態電路來達到高速的目的。然而在深次微米的製程下，漏電流除了會使鎖相迴路的效能降低外，更嚴重可能會造成數位動態電路的操作錯誤而讓鎖相迴路有錯誤的運作；此外，通道長度調變所產生的突波雜訊問題也是需要去注意的。在本論文第一部份中，先提出了自我治癒動態正反器的電路，此電路可以自行偵測正反器的輸出正確與否，一旦偵測到因為漏電流所造成錯誤的輸出，會立刻把漏電流抽走讓正反器繼續正確的運作。此外，漏電流和製程變異會使鎖相迴路中的壓控振盪器的操作頻率範圍和振幅變小，而我們在此也提出了一個針對壓控振盪器的自我治癒電路，此電路包括一個波谷偵測器和電流補償電路，其可以偵測壓控振盪器的振幅，當振幅不夠的時候進行電流補償，以達到寬範圍的操作頻率。接者介紹一個降低突波雜訊的電路，利用時間數位轉換器的概念，可以有效降低突波雜訊。最後在本論文中，我們針對鎖相迴路的鎖定時間來進行改善，利用頻率偵測電路和閘控制壓控振盪器大幅縮減鎖相迴路的鎖定時間。

關鍵字

漏流；快速鎖定

並列摘要

With the progress of the CMOS technologies, the demand of high-speed communication system grows gradually. The most important part of the communication system is clock system, which directly determines the speed and system performance. However, the leakage current problem in 90n or 65nm processes will degrade the performance of the clock systems, and the subject of this dissertation is to solve the problems of the clock generators in nanoscale processes. We propose the fast-locking phase-locked loop in the final part of the thesis. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed for the clock generations. PLLs are usually used in the high-speed applications due to their clock multiplication architecture. Thus, PLLs usually use the dynamic circuit to achieve the high-speed applications. However, in nanoscale processes, the large leakage current will degrade the performance of a PLL seriously. Furthermore, the leakage current may make digital dynamic circuits not to work properly. And the severe channel length modulation and the cirrent mismatch of the charge pump (CP) will produce large reference spur. These problems must be taken into account when the clock generators are implemented in nanoscale processes. In this dissertation, we propose the self-healing circuits for the dynamic TSPC. The self-healing circuits will detect the output of the TSPC. If it detects the malfunction of the TSPC, the self-healing circuits will counteract the leakage current and repair the state. Beside, the poor device matching and leakage current vary the common-mode voltage of a ring-based voltage-controlled oscillator (VCO) over a wide frequency range. It may limit the oscillation frequency range of a VCO and even causes a VCO not to oscillate. Here, we propose the self-healing circuits for the VCO. The circuits have the bottom-level detector to detect the swing voltage of the VCO and the current compensator. If the circuits detect the swing voltage too small to oscillate, it will compensate the current to the VCO. Furthermore, a digital technique is adopted to calibrate the current mismatch of the CP in phase-locked system. The amplitude of the reference spur can be reduced. Finally, we propose the fast-locking technique to reduce the locking time of the PLL by using the frequency detector circuits and the gated-ring-oscillator (GRO).

並列關鍵字

leakage ； fast-locking

參考文獻

[2] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw -Hill, 2001.

[6] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits”, Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.

[7] J. S. Chen and M. D. Ker, “Impact of gate leakage on performances of phase-locked loop circuit in nanoscale CMOS technology”, IEEE Transactions on Electron Devices, vol. 56, no. 8, Aug. 2009.

[8] C. Y. Kuo, J. Y. Chang, and S. I. Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer”, IEEE Trans. Circuits and Systems- I: Reg. Papers, vol. 53, no. 3, pp. 526-533, Mar. 2006.

[9] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider”, IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 378–383, Feb. 2004.

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具漏流補償和快速鎖定之鎖相迴路

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