一個每秒10億次取樣6位元48毫瓦類比數位轉換器

本研究是採用兩階段式 (Two-step) 的架構，來實現高速的類比數位轉換器(Analog-to-Digital Converter)。在此論文中提出一個快速穩定的方法 (fast-settling method)來縮短運算放大器的上升時間以及經由重新安排時脈圖來使得電路可以工作的更加有效率。本晶片使用台積電0.13-μm CMOS製程製作，解析度為六位元，操作時脈頻率為1 GS/s，INL為+0.3/-0.3 LSB，DNL為+0.49/-0.49 LSB，在輸入信號頻率為奈奎斯特頻率的情況下，SFDR為49.2dB，SNDR為31.3dB，在1.2伏特的供應電壓下，消耗功率為 50mW。

關鍵字

類比數位轉換器；兩階段式；時間交錯；低功率

並列摘要

A 1 GS/s 6-bit CMOS two-step ADC using fast-settling method and through timing rearrangement is demonstrated in a standard 0.13-μm CMOS process. The proposed method shortens the slew time of OPAMP in MDAC and the timing arrangement makes the circuits operated more efficient. The prototype circuit exhibits an INL of +0.3/-0.3 LSB and a DNL of +0.49/-0.49 LSB. The SNDR and SFDR achieve 31.3 and 49.2 dB at 1 GS/s for Nyquist input frequency. The ADC consumes 50 mW at 1.2V supply and occupies an active chip area of 0.16 mm2.

並列關鍵字

ADC ； Two-step ； Time-interleave ； low power

參考文獻

[1] B.Razavi, “Principles of Data Conversion System Design” Wiley-IEEE Press, 1995

[5] Chien-Kai Hung, Jian-Feng Shiu, I-Ching Chen and Hsin-Shu Chen “A 6-bit 1.6GS/s Flash ADC in 0.18-um CMOS with Reversed-Reference Dummy” IEEE Solid-State Circuits Conference, 2006 ASSCC, pages:335-338, Nov. 2006

[6] M. Flynn and D. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol.31, pp. 1248-1255, Sep. 1996

[7] Govert Geelen and Edward Paulus “An 8b 600MS/s 200mW CMOS Folding A/D Converter Using an Amplifier Technique” IEEE International Solid-State Circuits Conference, pp. 254-526, Feb. 2004

[8] Kurosawa. N, Kobayashi. H, Maruyama. K, Sugawara. H, Kobayashi. K, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 48, Issue 3, March 2001 Pages:261-271

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一個每秒10億次取樣6位元48毫瓦類比數位轉換器

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