時域分析之連續漸進式類比數位轉換器與每秒取樣10億次之6位元導管式類比數位轉換器

Time Analysis SAR ADC and 1GS/s 6Bits Pipelined ADC

吳逸翔(Wu,Yi Siang)

指導教授 ： 朱大舜

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

https://doi.org/10.6843/NTHU.2015.00403

摘要

隨著科技的進步，奈奎斯特類比數位轉換器不斷在操作速度與解析度上做改進，從快閃式類比數位轉換器、兩階段式類比數位轉換器、管線式類比數位轉換器至連續漸進式類比數位轉換器，其最終目標皆是在速度與解析度上找到一個完美的平衡。因此本論文題出了兩種高速類比數位轉換器的架構。

首先為一個時域分析模式下的連續漸進式類比數位轉換器，藉由線性的壓控時脈延遲與時間數位轉換器，在一開始的前七個位元取代了以往使用的電壓比較器，透過將各種輸入壓差的延遲時間差線性化後，再由時間數位轉換器找出輸入差值範圍，最後再回到連續漸進式類比數位轉換器輔以電壓比較器做最後五個位元的逼近，不僅大幅節省了連續漸進式類比數位轉換器其電荷重新分佈之次數，更提高傳統連續漸進式類比數位轉換器的操作速度並降低其耗能，並且為了降低因電容之間的匹配程度所產生的誤差，在最後的五個位元中加入了帶餘位元的機制，可在允許範圍內有效修正比較器因電容之間的不匹配所產生錯誤的判斷，提升類比數位轉換器的精準度。

最後則提出一前瞻的高速電流模式之導管式類比數位轉換器，其跳脫過去導管式類比數位轉換器常用的交換電容技巧，藉由電流鏡取代運算放大器的角色，使其不再受限於運算放大器的增益與操作頻率，大幅提升操作速度，並寄望未來能結合分時多工的技術，希望能在65奈米製程下達到4GHZ取樣速率、10位元解析精準度的目標。

關鍵字

類比數位轉換器 ； 時域分析 ； 連續漸進式 ； 導管式

並列摘要

As technology improve rapidly, the operation rate and resolution of Nyquist Analog to Digital Converter (ADC) are getting faster and higher. Such as Flash ADC、Two-stage ADC、Pipelined ADC and Successive Approximation Register ADC. There is only one goal, to make the operation rate and resolution matched perfectly. We propose two kinds of ADC’s architecture in this paper.

At first we propose a time analysis SAR ADC, which contain linear voltage control delay line and time to digital converter to replace voltage type comparator, get 7-bit resolution. The linear voltage control delay line take input signal difference as it’s input and generate delay time according to the amount of input signal difference linearly. After we get the delay time, time to digital converter can resolve it to digital thermal code. Thermal code go through an encoder change into binary code and send to control logic to make capacitor array subtract corresponding input signal difference, make input signal approach to each other rapidly. Which greatly reduce the operation time and the times of charge redistribution, save many power consumption. In order to improve the effect of capacitor mismatch, we add some redundant in the last 5-bit to calibration errors which cause by capacitor mismatch.

At last we propose a high speed current mode pipelined ADC, it’s unlike traditional architecture which often use switch capacitor to provide signal gain. We use current mirror to replace operational amplifier, which increase to operation speed and reduce gain error. In the future, this current ADC may combine with time interleaved technology accomplish a 4GS/s 10-bit ADC in tsmc 65nm process.

並列關鍵字

Analog to Digital Converter ； Time Analysis ； SAR ； Pipelined

參考文獻

1] G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August 2003.

[2] Goran Jovanović, Mile Stojčev, Dragiš Krstić: “Delay Locked Loop with Linear Delay Element”, in Proc. of 7-th International Conference TELSIKS, vol. 2, pp.397-400.

[3] G. S. Jovanović and M. K. Stojčev: “Current starved delay element with symmetric load”, International Journal of Electronics, pp. 167- 175, Vol. 93, No 3, March 2006.

[4] Dudeck P. et al., “A high–resolution CMOS time–to–digital converter utilizing a vernier delay line”, IEEE Journal of Solid–State Circuits, vol. 35, No. 2, pp. 240–246, February 2000.

[5] M. H. Chung, H. P. Chou, "A Time-to-Digital Converter Using Vernier Delay Line with Time Amplification Technique", Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 23-29 Oct. 2011, Hsinchu, Taiwan, pp. 772-775