一個低功率每秒兩億次取樣，十位元之管線式類比數位轉換器

在高速、中高解析度類比數位轉換器中，導管式的類比數位轉換器是最常使用一種方式。為了減低功率消耗，許多作品[1], [2], [3], [4]使用電容分享技術。傳統的電容分享技術使用了放電相位來取消回授電容上的電荷。但是放電相位占據放大相位的時間，使得功率消耗上升。此外，傳統的電容分享技術只有使用在第一級。這本作品，放電相位被移除，並且電容分享技術使用在第一級與第二級，所以功率消耗更進一步的減少。一個1.2V電壓，以90nm的類比數位轉換器在取樣頻率為200MS/s，輸入頻率為1.99MHz的情況下，SNDR為53.14dB。 MOS製程實現的一個每秒兩億次的導管式類比數位轉換器被提出來。在取樣頻率為200MS/s，輸入頻率為99MHz的情況下，SNDR為50.25dB，INL，DNL分別為+1.59/-1.91 LSB，+0.70/-0.75 LSB,。操作在電源電壓為1.2V時，功率消耗為45.4mW。類比數位轉換器所占的面積為0.53 mm2.

關鍵字

導管式類比數位轉換器；低功率；高速

並列摘要

In high speed, medium-high resolution analog-to-digital converter (ADC), the pipelined architecture is the most common used. To reduce the power consumption, the capacitor-sharing technique is used in [1], [2], [3], [4]. Conventional capacitor-sharing technique employed the discharge phase to cancel the charge on feedback capacitor. However, the discharge phase occupied the amplification phase, and power consumption is raised. In additional, conventional capacitor-sharing technique is also only applied in first stage. In proposed work, the discharge phase is removed, and capacitor-sharing technique is applied to first and second stage; hence the power consumption is further reduced. A 10-bit pipelined ADC with 1.2V, 200MS/s, in 90nm technology is proposed. In 200MS/s with 1.99MHz input, the signal to noise and distortion ratio is 53.14dB. In 200MS/s with 99.9MHz input, the SNDR is 50.25dB. Integral Nonlinearity and differential nonlinearity are +1.59/-1.91 LSB and +0.70/-0.75 LSB respectively. The power consumption is 45.4mW at 1.2V power supply. The ADC occupies an active area of 0.53 mm2.

並列關鍵字

pipelined ADC ； low-power ； high-speed

參考文獻

[1] B.G. Lee and R.M. Tsang, “A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-gm Opamp,” IEEE J. Solid-State Circuits, vol.44, pp. 883, Mar. 2009.

[2] N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, "A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback," IEEE J. Solid-State Circuits,vol.44,pp 2392,Sep.2009

[3] B.G Lee, B.M. Min, G. Manganaro, and J.W. Valvano, ”A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb 2008, pp. 224-225

[4] P. Y. Wu, V. S. L. Cheung, and H. C. Luong, “A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture,” IEEE J. Solid-State Circuits,vol. 42, pp. 730-738, Apr. 2007

[5] S.H. Lewis and H.S. Fetterman, "A 10-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol.27, no.3, pp.351-358, Mar 1992

國際替代計量

一個低功率每秒兩億次取樣，十位元之管線式類比數位轉換器

全文下載

主題瀏覽