P型氧化亞錫薄膜電晶體及其於互補式金屬氧化物電路之應用

P-type Tin Monoxide Thin-Film Transistors and Their Application in Complementary Metal-Oxide-Semiconductor (CMOS) Circuits

邱義忠(I-Chung Chiu)

指導教授 ： 陳奕君

國立臺灣大學/電機資訊學院/光電工程學研究所/博士(2014年)

https://doi.org/10.6342/NTU.2014.10874

摘要

本論文主要目的有兩個，一是研究與探討Ｐ型氧化亞錫薄膜及其薄膜電晶體之電性與電穩定性，另一則是進一步將Ｐ型氧化亞錫薄膜電晶體應用在互補式金屬氧化物薄膜電路中。近幾年，由於可攜帶式裝置的的快速發展，如何將系統電路整合於可攜式裝置的面板中，即面板系統（system-on-panel）之概念，吸引了許多人的廣泛研究與討論。透明金屬氧化物因具備可低溫成長、可大面積成長及高載子遷移率等特徵成為下世代面板的熱門候選材料之一。但常見的透明金屬氧化物多為Ｎ型半導體，而基本邏輯元件–互補式邏輯反相器則需同時具備Ｎ型與Ｐ型半導體電晶體元件，因此，製作與發展Ｐ型透明氧化物薄膜電晶體成為一重要課題。於本論文中，吾人利用金屬錫靶及射頻磁控濺鍍法來沉積透明Ｐ型氧化亞錫薄膜，並藉由製程參數之調變來對其對氧化亞錫薄膜及其薄膜電晶體元件進行最佳化。本論文亦採用高介電常數之材料–氧化鉿作為薄膜電晶體元件之閘極介電層，藉以降低薄膜電晶體元件之操作電壓並改善電晶體特性。所製作100奈米厚之Ｐ型氧化亞錫薄膜穿透率約為60%左右，其霍爾載子遷移率最高可達1.5 cm2/V-s，而薄膜電阻率則介於5
~30 Ω-cm 間。研究中所開發之Ｐ型氧化亞錫薄膜電晶體之臨界電壓約為3~5 V間，載子遷移率約為0.2~0.78 cm2/V-s 間，次臨界擺幅約為1.6~3V/decade 間，開關比約為103~8.1×104 間。吾人進一步將Ｎ型氧化鋅薄膜電晶體及Ｐ型氧化亞錫薄膜電晶體整合，製作出互補式薄膜反相器電路，在供給電壓為10 V 時，其信號增益值可達17V/V，且具高的雜訊邊限。最後，藉由串聯上述之反相器，成功製作出氧化物半導體環形震盪器，其震盪頻率約為2k Hz。

關鍵字

Ｐ型氧化物 ； 薄膜電晶體 ； 電路

並列摘要

There are main two objectives in this dissertation. One is to investigate theelectrical performance and electrical bias-stress stability of p-type SnO thin-film transistors (TFTs); the second is to further develop complementary metal-oxide semiconductor (CMOS) circuits by using the p-channel SnO TFTs. In recent years, the concept of system-on-panel, in which the circuits are integrated into the panel of mobile electronics, has attracted great attentions and motivates study in the related fields. Metal-oxide semiconductor (MOS) are one of the candidates for the next
generation of displays due to possessing several advantages. These include high carrier mobility, being capable of large-area deposition, being capable of low temperature processing and several others. However, most oxide semiconductors are n-type. To realize the complementary metal-oxide semiconductor (CMOS) inverter, which is the building block of integrated logic circuits. It is important to develop the p-type oxide TFTs. In this work, the transparent SnO thin films are deposited reactive RF sputtering using a metal Sn as the target. The effect of various process parameters on both electrical properties of SnO thin films and the electrical performance of SnO TFTs was studied. High-k dielectric HfO2 was introduced as the gate dielectrics to both reduce the operating voltage and improve the electrical performance of the SnO TFTs. The optical transmittance for the 100 nm-thick SnO thin films was about 60%. The resistivity of the SnO thin film ranged from 5 to 30 Ω-cm, and the maximum Hall mobility of the SnO thin films was about 1.5 cm2/V-s. The fabricated SnO TFTs exhibited threshold voltages of 3 ~ 5 V, linear field-effect mobilities of 0.2 ~ 0.78 cm2/V-s, sub-threshold swings of 1.6 ~ 3 V/decade, and on/off ratios of 103 ~ 8.1×104. A CMOS inverter based on n-channel ZnO and p-channel SnO TFTs are demonstrated. A static gain of 17 V/V at a supplied voltage (VDD) of 10 V and a balanced noise margin was obtained. Finally, a ring oscillator composed of the above CMOS inverters was demonstrated and showed an oscillation frequency of 2 kHz

並列關鍵字

p-type oxide semiconductor ； thin film transistor ； circuit

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