應用於低電壓大電流負載的直流-直流轉換器之電源管理技術

Power Management Techniques in DC-DC Converters for Low-voltage and High-current Loads

丁中一(Chung-Yi Ting)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2019年)

https://doi.org/10.6342/NTU201901716

摘要

科技日新月異，像是5G通訊、大數據、物聯網、人工智慧興起。未來，各種不同應用會大量需要高速電腦運算能力與高速資料傳輸速度。因此，高速類比與數位電路在高速運算與高速傳輸介面扮演關鍵角色。根據摩爾定律發展，半導體製程技術不斷進步，使得電路的供應電壓不斷往下降。為了提升性能，電子元件的功耗卻不斷上升。因此，近年來應用於低電壓大電流負載直流-直流轉換器成為研究重點。在低電壓大電流應用下，負載可區分為高速數位電路與高速類比電路兩種。高速數位電路有中央處理器(CPUs)、圖形處理器(GPUs)、人工智慧運算晶片(AI chips)等；而高速類比電路有高速無線傳輸器(High-speed RF transmitters)、高速無線接收器(High-speed RF receivers)、高速數位類比轉換器(High-speed digital-to-analog converters)、高速類比數位轉換器(High-speed analog-to-digital converters)、光通訊電路(Optical communication circuits)等。這些高速電路需要具快速的暫態響應、低電磁干擾、大電流承載能力、與高轉換效率的直流-直流轉換器。傳統解決方案使用線性穩壓器(Low dropout regulators)，達到快速暫態響應能力、與低漣波輸出(Low-ripple output voltage)的電源。但線性穩壓器不適合高功率應用，而且線性穩壓器受限於最小電壓差(Dropout voltage)，會導致在高功率應用下轉換效率不高。為了在高功率應用下達到快速暫態響應、快速動態調節響應、大電流承載能力、高轉換效率、與低電磁干擾，本論文聚焦於低電壓大電流負載的直流-直流轉換器之電源管理技術相關研究。本論文所發展的電源管理技術有以下三個部份：
第一部份為了提升直流-直流轉換器的暫態響應速度與動態電壓調整響應速度，因此提出應用於射頻電路下最適定導通時間控制之類電壓平方磁滯控制降壓型直流-直流轉換器。為了實現最適定導通時間控制(Adaptive constant on-time control)，本論文提出具暫態加速技術的最適定導通時間電路，並對系統補償進行最佳化，以達到高速暫態響應與高速動態電壓調整響應。本晶片採用台積電T18 1P6M製程，面積1.81mm2，最高轉換效率為90.1%。藉由晶片量測結果，當負載電流往上變化600mA，回復時間為0.6μs；當負載電流往下變化600mA，回復時間為0.6μs。而參考電壓從1.8跳升到2.4V，輸出電壓響應速度為2μs；參考電壓從2.4V跳降1.8V，輸出電壓響應速度為2μs。
第二部份為了提高直流-直流轉換器的電流承載能力與轉換效率，因此提出具電感電流均流校正技術之快速延遲鎖定迴路應用於固定導通時間控制之四相位降壓型直流-直流轉換器。本晶片除了採用類電壓平方控制與固定導通時間調變之外，也採用延遲相位鎖定迴路產生四相位的脈波控制訊號且彼此錯相九十度，達到低漣波輸出電壓。為了達到快速暫態響應能力，本研究提出一組自動切換單/雙向觸發相位偵測器(Automatically switching single/dual triggered phase detector)應用於快速延遲鎖定迴路(Fast-locking delay-locked loop)。此外，為了解決主、被動元件的非理想效應所造成多相位電感電流不均流問題，本論文提出脈波縮減電路(Pulse-width-shrunk technique)進行均流背景校正。本晶片使用台積電T18 1P6M製程，面積6.17mm2。最後透過後模擬驗證結果，當負載電流往上變化1.4A，回復時間與電壓降為2.5μs/6.5mV；當負載電流往下變化1.4A，回復時間與電壓升為2.5μs/8mV。因為四相位均流且正確錯相九十度，最高效率達85%且輸出電壓漣波為4mV。
第三部份為了解決電磁干擾問題，因此提出具抗電磁干擾之類電壓平方磁滯控制降壓型直流-直流轉換器。傳統類電壓磁滯控制降壓型轉換器可視為一組壓控振盪器(Voltage control oscillator)。為了定頻控制，將傳統類電壓磁滯控制降壓型轉換器結合鎖相控制迴路。本論文的抗電磁干擾技術是整合鎖相控制迴路(Phase-locked loop)與全數位二級一階和差積分調變器(MASH 1-1 all-digital Δ-Σ modulator)，將脈波控制訊號的頻率進行調變，使得輸出電壓頻譜達到展頻效果。此晶片採用台積電T18 1P6M製程，面積1.81mm2，最高轉換效率為90%。透過後模擬驗證，展頻前後頻譜改善20dB。當負載電流往上變化500mA，回復時間與電壓降為4.47μs/34.3mV；當負載電流往下變化500mA，回復時間與電壓降 5.12μs /32.3mV。

關鍵字

低電壓大電流負載 ； 固定導通時間控制 ； 類電壓平方磁滯控制 ； 多相位直流-直流降壓型轉換器 ； 電感電流均流校正技術 ； 全數位二級一階和差積分調變器

並列摘要

Science and technology rapidly progress day by day, such as 5G communication, big data, internet-of-things (IoT), artificial intelligence (AI). In the future, these computers with high-speed computing ability and high-speed data transmission are needed in various applications. Therefore, high-speed integrated circuits are very important in high-speed computing and data transmission interface. In addition, the supply voltage becomes lower and lower because the technology process is rapidly advancement based on Moore’s law. However, power consumption of electronic devices constantly increase for higher performance. Thus, these DC-DC converters in low-voltage and high-current applications are essential research topic in recent years. In low-voltage and high-current applications, these loads have two categories about high-speed digital circuits such as CPUs, GPUs, and AI chips and high-speed analog circuits such as high-speed RF transmitters, high-speed RF receivers, high-speed DACs, high-speed ADCs, and optical communication circuits. In general, these high-speed circuits need to the DC-DC converter with fast load-transient response, low EMI, high-current capability, and high-efficiency. Traditionally, low-dropout regulators (LDOs) have been used in on-chip voltage source because of load-transient response and low-ripple output voltage. However, LDOs are not suitable for high power applications because the dropout voltage leads to low efficiency in low-voltage and high-current applications. To achieve fast load-transient response, fast DVS tracking response, high-current capability, high power efficiency, and low EMI in high power application, the dissertation focuses on studying power management techniques of these DC-DC converters in low-voltage and high-current applications. The dissertation has three works:
In the first work, we propose a quasi-V2 hysteretic buck converter with adaptive constant on-time (ACOT) control for fast DVS and load-transient response in RF applications. For implement adaptive constant on-time control, the work proposes adaptive constant on-time circuit with transient-enhanced technique and optimization of system compensation for fast load-transient response and fast DVS. The work uses TSMC T18 1P6M process and chip area is 1.81mm2. The measured peak efficiency is 90.1%. In 600mA step-up/down load current, the light-to-heavy/heavy-to-light recovery time is 0.6μs. In 0.6V voltage step-up/down, the up-tracking/down-tracking time of DVS is 2μs.
In the second work, we propose an inductor current-balancing technique (ICBT) for fast-locking delay-locked loop (FL-DLL) based four-phase buck converter with constant on-time control to achieve high-current capability and power efficiency in low-voltage and high-current applications. The work uses quasi-V2 control and constant on-time modulator for transient response and light-load efficiency. Moreover, the work proposes a fast-locking delay-locked loop (FL-DLL) for generating four-phase control signals with phase difference 90 degree and achieving low-ripple output voltage. In FL-DLL, we proposes automatic switching single/dual triggered phase detector (ASS/DT-PD) for achieving fast load-transient response. Furthermore, non-ideal effects of active and passive components causes inductor current in-balance issue. Therefore, the work proposes pulse-width-shrunk technique (PWST) automatically calibrate four-phase control signals to achieve current balance in every phase. The work uses TSMC T18 1P6M process and chip area is 6.17mm2. Finally, these proposed techniques can be verified by post-layout simulation. In 1.4A step-up/down load current, the light-to-heavy/heavy-to-light recovery time is 2.5μs/2.5μs and undershoot/overshoot voltage is below 10mV. Because of achieving current balance and phase alignment, the proposed FL-DLL based four-phase buck converter has 85% efficiency and 4mV voltage ripple.
In the third work, we propose a quasi-V2 hysteretic buck converter with EMI reducing technique using phased-locked loop with MASH 1-1 all-digital Δ-Σ modulator. The hysteretic DC-DC buck converter is viewed as voltage control oscillator (VCO). For keeping fixed-frequency, the work uses phase-locked loop to lock PWM frequency. In the EMI reducing technique, phase-locked loop with MASH 1-1 all-digital Δ-Σ modulator randomly modulates PWM control signal for spreading spectrum of output voltage. The chip uses TSMC T18 1P6M process and chip area is 1.81mm2. Moreover, the measured peak efficiency is 90%. By post-layout simulation, the low EMI reducing technique improves 20dB compared with without EMI technique. In load-transient response performance, the light-to-heavy recovery time is 4.47μs and undershoot voltage is 34.3mV and the heavy-to-light recovery time is 5.12μs and overshoot voltage is 32.3mV.

並列關鍵字

Low-voltage and high-current loads ； Constant on-time control ； Quasi-V2 hysteretic control ； Multi-phase DC-DC buck converter ； Inductor current-balancing calibration technique ； MASH 1-1 all-digital Δ-Σ Modulator

參考文獻

[1]P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-type III compensation,” IEEE J. of Solid-State Circuits, vol. 45, no. 8, pp. 1446–1455, Aug. 2010.

[2]M. Ho, J. Guo, K. H. Mak, W. L. Goh, S. Bu, Y. Zheng, X. Tang, and K. N. Leung, “A CMOS low-dropout regulator with dominant-pole substitution,” IEEE Trans. on Power Electronics, vol. 31, no. 9, pp. 6362–6371, Sept. 2016.

[3]J. Y. Lee, S. E. Kim, S. J. Song, J. K. Kim, S. Kim, and H. J. Yoo, “A regulated charge pump with small ripple voltage and fast start-up,” IEEE J. of Solid-State Circuits, vol. 41, no. 2, pp. 425–432, Feb. 2006.

[4]K. H. Chen, Power Management Techniques for Integrated Circuit Design, NJ: John Wiley & Sons, 2016.

[5]C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS dc-dc converter with on-chip current-sensing technique,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004.