新型電流模式直流-直流降壓轉換器與負電壓低壓降電壓調整器之研製

Design and Implementation of New On-Chip Current-Mode DC-DC Buck Converter and Low-Dropout Voltage Regulator with Negative Input-Output Voltage

陳彥名(Yen-Ming Chen)

指導教授 ： 陳建中 ； 黃育賢

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2007年)

https://doi.org/10.6841/NTUT.2007.00274

摘要

本論文的第一個部份，提出一個運用磁滯電流控制機制取代傳統斜率補償的新型降壓電路。由於所提出的電流感測電路不僅可以全時間感測電感電流和控制降壓電路，而且結構簡單、只用到極少的元件，故在設計上十分容易。而所採用的磁滯電流控制機制在工作週期(Duty Cycle)超過50%時，既使不使用斜率補償亦可有效防止電路產生次諧波震盪(Subharmonic Oscillation)的問題。本電路使用的是台積電0.35μm互補式金氧半製程，晶片面積為2.33 mm2。
本論文的第二部份是針對負電源系統所中需要的負電壓低壓降電壓調整器(LDO)提出設計與實現。其控制機制是根據輸出電壓與輸入參考電壓的差值電壓，在經過放大之後，藉由控制功率電晶體的閘極電壓，與流過負載的輸出電流，使輸出電壓受到控制。最後，輸出電壓再與電壓調整器的負端相連，使整個系統形成穩定的負回授系統，因此輸出電壓是可被預先設計以及固定的。本電路使用的是台積電0.35μm互補式金氧半製程，晶片面積為0.45 mm2。

關鍵字

磁滯電流控制 ； 直流對直流轉換器 ； 電流感測 ； 低壓降電壓調整器 ； 等效串聯電阻

並列摘要

In the first part of this thesis, we present an integrated buck converter using hysteresis current controlled (HCC) techniques without slope compensation. The proposed current sensing circuit is very simple and only consists of few components, which can be designed easily. The designed buck converter using the current sensing circuit and HCC techniques can be stable even if the duty cycle is greater than 50%. The buck converter is implemented with 3.3-V TSMC 0.35μm CMOS DPQM processes, and the chip area is 2.33mm2 with PAD.
In the second part of this thesis, we present a low-dropout linear regulator (LDO) with negative in-out voltage. The characteristic of proposed LDO is its very low quiescent current and ultra high DC gain. Therefore, the line/load regulation of designed LDO is great than other design. The LDO is implemented with 3.3-V TSMC 0.35μm CMOS DPQM processes, and the chip area is 0.45mm2 with PAD.

並列關鍵字

hysteresis-current controlled ； dc-dc converter ； current sensing ； low-dropout linear regulator ； equivalent series resistance

參考文獻

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