雙向晶片網路架構之效能感知程序映射

Performance-aware Task Mapping for Bi-directional NoC Architecture

林玥其(Yueh-Chi Lin)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10448

摘要

本文針對雙向晶片網路架構(bi-dirctional NoC)提出一個效能感知程序映射演算架構，包含程序叢集(task clustering)及程序映射(task mapping)兩個演算法。利用雙向晶片網路架構的資料傳送通道可被調控之特性，在各個時間點分配通道給需要的資料流，以達到提升系統效能之效果。實驗結果顯示本文所提出之效能感知程序映射演算架構可有效降低系統之執行時間，提升系統在雙向晶片網路架構上之效能。

關鍵字

雙向晶片網路架構 ； 晶片網路架構 ； 映射

並列摘要

In this Thesis, we propose a performance-aware task mapping algorithm for BiNoC (bi-directional network-on-chip) architecture. The whole framework contains two phases: task clustering and task mapping. For a given task graph and a BiNoC topology, the task clustering phase partitions a task graph into appropriate clusters to minimize the system parallelization time. The task mapping phase employs an SA-based (simulated annealing-based) algorithm which maps clusters of TCG (task communication graph) to PEs (processing elements) injectively. The SA-based algorithm uses real execution time as the cost function and considers the negative effect caused by contentions. Since the channel direction is configurable in a BiNoC, our approach makes use of this characteristic to allocate channel admission to the communication demands and lead to a low system execution time. Experimental results show that, compared to other existing mapping approaches for performance-aware purpose, our approach achieves a significant decrease in packet latency.

並列關鍵字

bi-directional NoC ； BiNoC ； NoC ； mapping

參考文獻

[1] Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu-Hen Hu, and Sao-Jie Chen, “BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,” Proc. of ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 266-275, May 2009.

[2] Chen-Ling Chou and Radu Marculescu, “Contention-aware Application Mapping for Network-on-Chip Communication Architectures,” Proc. of IEEE International Conference on Computer Design (ICCD), pp. 164-169, Oct. 2008.

[3] Tang Lei and Shashi Kumar, “A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture,” Proc. of Euromicro Conference on Digital System Design (DSD), pp. 180-187, Aug. 2003.

[4] Jingcao Hu and Radu Marculescu, “Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures,” Proc. of Conference on Design, Automation & Test in Europe (DATE), pp. 688-693, Apr. 2003.

[5] Jingcao Hu and Radu Marculescu, “Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints,” Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp.233-239, Jan. 2003.