晶片網路之多核心平台之應用層級追蹤器設計

Application-Level Transaction-Based Trace Infrastructure for NoC-Based Many-Core Platform

黃慶立(Ching-Li Huang)

指導教授 ： 黃稚存

國立清華大學/電機資訊學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6843/NTHU.2013.00149

摘要

在現今的VLSI設計，多核心處理器常被整合進單一的系統晶片(SoC)，網路晶片系統(NOC)被視為是一個有效應用於處理器之間的傳輸方法，由於核心的數目隨著製成的進步不斷急遽提高且日趨複雜，有效的驗證及偵錯核心之間的傳輸問題變成一個很重要的議題，考慮到這原因，我們將重點放在追蹤和除錯核心之間的傳輸。
本篇論文裡，我們提出了應用於晶片網路之多核心平台的應用層級追蹤器，每個追蹤器會監測處理單元(Processing Element)裡的系統匯流排，我們提出的追蹤器是由可設定即時匯流排追蹤器和OCC辨認元件(On-Chip Communication Recognition Unit) 所組成。在OCC辨認元件下，我們的方法是應用層級的追蹤方式，透過追蹤即時的匯流排資料偵測特殊的觸發事件，因此，匯流排資料只在事件觸發時被追蹤出來。為了解決核心之間的傳輸問題，我們的觸發事件是根據軟體端的資料傳輸協定和一些重要的目標暫存器所定義，追蹤出來的底層硬體信號會進一步的被轉換成較高層級的訊息，可有效的開發、驗證、偵錯與追蹤實際的系統應用，以利於達到軟硬體整合。我們也提供了離線端的語法分析器，分析追蹤出來的資料，將資料還原成每個核心傳輸的過程，如此可提供最直接的資訊給使用者。除此之外，我們也提出了一個標準的偵錯流程，可以使用在不同層級的多核心系統平台。透過我們提出的流程和追蹤器幫助，可以有效率的進行核心之間的傳輸偵錯，並了解傳輸效率。
在我們的工作中，SystemC平台被採用於分析OCC辨認元件的行為，電子系統層級的SystemC平台可提將週期層級提升到交易層級以增加系統模擬的速度。根據系統模擬的實驗，我們所提出的應用層級的追蹤方式比交易層級有效地減少99.6%的追蹤資料，比較於信號層級有效地減少99.7%的資料量。
最後，我們舉例了以些常見的傳輸，來介紹如FIFO大小、和快取機制等等會導致多核心平台上傳輸的錯誤的重要議題。

關鍵字

多核心系統 ； 應用層級追蹤器 ； 網路晶片 ； 軟硬體整合

並列摘要

In the modern SoC, multiple processors are commonly integrated into the single chip. Network-On-Chip (NOC) is considered as a promising solution for on-chip inter-core communication. Owing to the rapidly increasing number of processors, verification and debugging of the inter-core communication has become one of the most important issues to be taken into consideration. As the reason, we put emphasis on the trace and debug for the inter-core communication issues.
In the thesis, we proposed an application-level transaction-based trace infrastructure for NoC-based many-core platform which monitors the local bus in each processor element (PE). The proposed trace infrastructure is composed with the configurable real-time bus tracer and the proposed On-Chip Communication (OCC) Recognition Unit.
The trace method in OCC Recognition Unit is based on the event-based application level trace. In order to solve the inter-core communication problem, the specific events are defined according to the data transmission protocol and the value of target registers. Thus, the monitored bus signals are traced only when the specific event occurs. Furthermore, the complex lower level hardware signals are converted to an application-level data corresponding to the occurrence of pre-define event.
We also provide the off-line parser to parse the trace data to restore the progress of transmission and provide the direct information to the software programmer. In addition, the debugging flow is proposed which can be adopted in different level of many-core systems to debug the inter-PE communication problem efficiently with the aid of proposed trace infrastructure.
In our work, the SystemC platform is adopted to do cross-verification and to analyze the behavior of the On-chip Recognition Unit. It can raise the cycle-based level to higher transaction-based level, so it provides faster simulation speed.
With the data size comparison experiment, the size of traced data with application level trace can be significant reduced by 99.6% as compared with the transaction level trace and 99.7% as compared with the signal level trace. For demonstrating the capability of debugging and diagnosing, we adopted two typical user cases to introduce the FIFO full issue and cache miss coherency issue which are important common issues on many-core platform that may cause the inter-PE communication failure.

並列關鍵字

many-core platform ； NoC ； Bus tracer ； Hardware/Software Co-Design ； application level trace ； System-Level Debug

參考文獻

[2] P.-Y. Chen and C.-T. Huang, "RTL Realization of NoC-Based Multi-Core Platform", in Master Thesis, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, Oct. 2011.

[5] OCP International Partnership, Open Core Protocol Specification.

[7] Shan Tang, Qiang Xu, "In-band cross-trigger event transmission for transaction-based debug", in Proc. Design, Automation, and Test in Europ (DATE), Mar. 2008.

[16] OCP-IP, "Open core protocol specification release 2.2", http://www.ocpip.org, Jan. 2007.

[1] DAFCA, "On-chip, at-speed, debug and DFT support for OCP-based SoC's", in Proc. Design, Automation, and Test in Europ (DATE), 2006.