矽基分散式放大器之研製

隨著傳遞大量資料需求的升高，高速傳輸系統的發展也漸趨熱門。在光纖系統中扮演重要角色的寬頻放大器，由於頻寬的需求，常可見利用可克服增益頻寬乘積限制的分散式架構來設計製作。光纖傳輸系統發展以來已有一段時間，早期為了因應高速的設計，多採用如砷化鎵或是磷化銦此類先進製程。可惜的是這樣的製程成本較高，且不適合進行晶片系統的整合。近年來，矽基光電積體電路(OEISs)的研究提供了寬頻放大器製作上的另一種選擇，隨著半導體製程的演進，未來的發展極具潛力，因此我們選擇了矽基的分散式放大器(DAs)作為本論文研究及探討的主題。設計分散式放大器的過程中，通常會應用到許多電感或是傳輸線。在矽基製程中，此類元件的低品質因素和高損耗矽基版是主要的障礙之一。在論文設計中，我們採用金屬線來實現大部分的電感以解決電感自振並克服頻寬問題，如此的結構亦降低基板損耗。而在螺旋電感部份則進行實際量測以求電路精確性。傳統式的設計方法對於分散式放大器來說，經由基本理論推導得知其有一定的增益頻寬乘積限制。除了上述被動元件的損耗問題，在CMOS中，主動元件本身的閘極端與汲極端等效輸入寄生電容較大，使得有效頻寬縮小，且較小的轉導值也是一個不利利用CMOS設計分散式放大器的原因，而SiGe HBT中，基極端較大的等效寄生阻抗亦降低其電路特性。針對以上特性，我們提出一CMOS摺疊式分散式放大器，其量測頻寬由6GHz至32.5GHz，增益值5±1.15dB。經由第一顆晶片的討論和檢討，我們更仔細的設計了一模擬頻寬由0.9GHz至33.3GHz，而增益值9±0.9dB的CMOS分散式放大器。最後，我們再次提出一利用射極負反饋和自偏壓的SiGe HBT分散式矩陣放大器，其模擬頻寬可至49GHz，增益值9.5±0.5dB。

關鍵字

增益頻寬乘積；矽基；傳輸線；分散式放大器；寄生電容

並列摘要

As the demands for broadband communication continue to expand, the development of high-speed data link has attracted great attention recently. With the requirement of operating bandwidth, the distributed amplifier is the most widely used topology to overcome the limitation of gain-bandwidth product. In the choice of process technology, compound semiconductors such as GaAs or InP are preferable due to the superior high-speed characteristics of the transistors Unfortunately, these processes have higher cost and are not suitable of chip system integration. The recent advance in CMOS and BiCMOS process technologies motivates the study of silicon-based optoelectronic integrated circuits due to the lower cost and higher level of system integration. Therefore, the circuit implementation of Si-based distributed amplifier is chosen as the topic of this thesis. In the design of distributed amplifiers, the inductors or transmission lines are required to construct the signal propagation paths at input and output. The inherently low quality factors of the passive components have long impeded the implementation of Si-based distributed amplifiers. In this thesis, the characteristics of the passive components have been studied and modeled for the optimization of the distributed amplifiers. From theoretical analysis, the gain-bandwidth product of distributed amplifiers with conventional architecture has been limited by the fmax of active devices. In a CMOS technology large parasitic capacitance in gate and drain terminal of active devices leads to a smaller bandwidth while the low transconductance imposes strict restrictions on the overall gain of the distributed amplifiers. On the other hand, the large equivalent parasitic impedance at the base of bipolar devices degrades the circuit performance in a BiCMOS technology. In order to alleviate the design issues, a CMOS folded distributed amplifier is first proposed to optimize the bandwidth. It exhibits a power gain of 5±1.15dB within the frequency range from 6GHz to 32.5GHz. In the second design, another CMOS distributed amplifier is designed for high power gain. The simulated gain and bandwidth are 9±0.9 dB and 3.3GHz, respectively. Finally, effort has been made for the design of a SiGe HBT matrix distributed amplifier using emitter degeneration and self-bias technique, achieving a gain of 9.5±0.5 dB and a bandwidth of 49GHz.

並列關鍵字

parasitic capacitance ； transmission line ； Distributed amplifier ； gain-bandwidth product ； silicon-based

參考文獻

[1]Thomas T. Y. Wong, “Fundamentals of Distributed Amplification”

[5]D. Lovelace, J. Costa and N. Camilleri, “Extracting small-signal mode parameters of silicon MOSFET transistors,” IEEE MTT-S Int. Microwave Symp. Dig., pp. 865-868, 1994.

[6]David M. Pozar, “Microwave Engineering”, Second Edition.

[7]Ballweber, B.M.; Gupta, R.; Allstot, D.J., “A fully integrated 0.5-5.5 GHz CMOS distributed amplifier” Solid-State Circuits, IEEE Journal of , Volume: 35 , Issue: 2 , Feb. 2000 Pages:231 - 239

[9]Ren-Chieh Liu; Kuo-Liang Deng; Huei Wang, “A 0.6-22-GHz broadband CMOS distributed amplifier,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE , 8-10 June 2003 Pages:103 – 106

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矽基分散式放大器之研製

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