應用於K頻段與超寬頻之矽基低雜訊放大器的研製

Design of Silicon-Based Low Noise Amplifiers for K-Band and Ultra-wideband Applications

忻士傑(Shih-Chieh Shin)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.01550

摘要

隨著無線通訊技術的蓬勃，射頻積體電路正朝向更高頻率、更廣頻寬及與基頻電路更高的整合度之趨勢發展。在無線通訊接收前端電路中，低雜訊放大器將天線接收到的微弱訊號以最低的雜訊貢獻加以放大。矽基製程(包括金氧半互補式(CMOS)製程與矽鍺雙極-金氧半互補式(SiGe BiCMOS)製程)，都可將基頻數位電路、中頻類比電路及射頻前端電路整合於同一矽晶片上，進而降低生產成本。然而，相較於砷化鎵(GaAs)製程，矽基板的半導體特性導致更多的雜散電容，以及隨著頻率增加損耗更為嚴重，同時也較難預測被動元件在高頻的特性。即使有這些困難，為了達到低成本高整合性的無線通訊系統，使得近年來矽基射頻積體電路成為一個熱門的研究課題。
在本論文中，我們設計並量測了兩個操作於K頻帶的CMOS低雜訊放大器。第一個低雜訊放大器使用標準0.18-μm CMOS 製程，此設計的最大挑戰是其操作頻率僅為最大振盪頻率之半。我們使用適當的匹配電路設計達到良好的雜訊指數及小訊號增益。此低雜訊放大器經由量測可得在24GHz，雜訊指數為3.9 dB，小訊號增益為13.1 dB，直流功率為14 mW，晶片面積僅0.34平方毫米。另一個電路使用先進的90奈米CMOS製程。然而，此新製程的變異與不確定性也較大。為了克服此問題，我們使用共面波導(Coplanar Waveguide, CPW)傳輸線作為匹配元件，以減低損耗性基板對被動元件的影響，減少被動元件模擬的不確定性，同時，寬頻的電路設計可容忍較大的製程變異。量測結果顯示，此電路在20.5 GHz具有最高增益16.2 dB，3-dB頻寬可涵蓋整個K頻帶(18-26 GHz)，雜訊指數最低為2.5 dB。這兩個電路的雜訊指數皆優於目前已發表之CMOS K頻帶低雜訊放大器，並顯示出CMOS製程於高頻低雜訊應用的潛力。
最後一個電路是應用於超寬頻系統的低雜訊放大器。此電路使用0.35-μm SiGe BiCMOS製程，其所提供之異質接面雙極電晶體，具有良好的轉導對電流比(transconductance to current ratio, gm/IC)。使用分散式放大器的架構，可達到寬頻特性與良好的回返損耗。使用一個額外的電感並聯於集極端終端電阻，可將分散式放大器的頻率響應由低通轉為適合超寬頻系統的帶通，同時提供了另一條直流迴路使集極電流繞過終端電阻，可降低供應電壓。另外，使用可調式的終端電阻，可以補償不同偏壓下發生於終端電阻的負載不匹配效應，達到良好的增益平坦度。根據量測結果，此電路在0.8 V的供應電壓下，可達到12 dB的小訊號增益，3-dB頻寬為1.6-12.1 GHz，雜訊指數低於6.5 dB。藉由調整適當的終端電阻，在最高增益20 dB到最大衰減18 dB的範圍內，在3.1-10.6 GHz頻帶內增益的變異都小於 1 dB。

關鍵字

矽基 ； K頻段 ； 超寬頻 ； 低雜訊放大器

並列摘要

With the development of wireless communication technologies, RF integrated circuits move toward higher frequencies, wider bandwidth, and higher integration level with baseband circuits. In wireless communication receiver front-ends, low noise amplifier (LNA) is used to amplify the weak signal from the antenna with minimum noise contribution. Silicon-based technologies, including CMOS and SiGe BiCMOS, can integrate the baseband digital, IF analog, and RF front-end circuits on the same die, thereby reducing the production cost. However, compared to GaAs processes, the inherent semiconductor properties of the silicon substrate result in high parasitic capacitance, higher loss with increasing operating frequency and difficult prediction of passive elements at high frequency. Despite these difficulties, Si-based RFIC is still an active research topic in recent years for low-cost and high-integration wireless communication systems.
In this thesis, two CMOS LNAs operating at K-band were developed. The first LNA is implemented in a standard 0.18-μm CMOS technology. The major challenge of this circuit is that the operating frequency is almost half of fMAX. Proper design of matching networks leads to good noise and gain performances. The measured NF is 3.9 dB and the small signal gain is 13.1 dB at 24 GHz. The dc power consumption is 14 mW. The chip size is only 0.34 mm2. Another circuit is fabricated in an advanced 90-nm bulk CMOS process. However, the new technology also has higher process variation and modeling uncertainty. In order to overcome these problems, coplanar waveguide (CPW) transmission lines are used as matching elements to reduce the effect of lossy substrate. The circuit is also designed to have a wide-band frequency response to tolerate process variation. The measured small signal gain is 16.2 dB at the peak gain frequency of 20.5 GHz with a 3-dB frequency band from 18 to 26 GHz. The minimum NF is 2.5 dB. Both LNAs reveal lower noise figure compared with published works of CMOS LNAs operating at frequencies around 20 GHz.
Another LNA is designed for ultra-wideband (UWB) applications. The circuit is fabricated in a 0.35-μm SiGe BiCMOS technology. The hetero-junction bipolar transistor (HBT) provided in this process has a good transconductance to current ratio (gm/IC). Based on the architecture of the distributed amplifier, wide band performance with good return losses can be obtained. An additional inductor in parallel with the termination resistor is used to transfer the frequency response from a low-pass to a band-pass response and to provide another dc path for the collector current to bypass the termination resistor. Therefore a lower supply voltage can be used. The termination resistor is replaced by a variable resistance FET. Different resistances are selected for different bias conditions to reduce the load mismatch effect and lead to good flatness of gain response. The measured small signal gain is 12 dB with a 3-dB frequency band from 1.6 to 12.1 GHz under the power consumption of only 6.4 mW. The noise figure is lower than 6.5 dB. The gain control range is about 38 dB with maximum gain of 20 dB and maximum attenuation of 18 dB. At these gain levels, the maximum gain variation from 3.1 to 10.6 GHz is about 1 dB.

並列關鍵字

Silicon-Based ； Low Noise Amplifier ； K-Band ； Ultra-wideband

參考文獻

[1] X. Guan and A. Hajimiri, "A 24-GHz CMOS front end," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 368-373, Feb. 2004.

[3] A. Bevilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receiver,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp.382-383.

[4] A. Ismail and A. Abidi, “A 3 to 10 GHz LNA using a wideband LC-ladder matching network,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp.384-385.

[5] S. Andersson, C. Svensson, and O. Drugge, “Wideband LNA for multi-standard wireless receiver in 0.18 μm CMOS,” in Proc. ESSCIRC, Sep. 2003, pp.655-658.

[6] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “A low supply voltage SiGe LNA for Ultra-Wideband frontends,” IEEE Microwave And Wireless Components Lett., vol. 14, no. 10, pp. 469-471, Oct. 2004.