超寬頻低雜訊放大器與 K 頻帶功率放大器之設計與實現

Design and Implementation of UWB Low Noise Amplifier and K-Band Power Amplifier

王怡惠(Yi-Huei Wang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系通訊工程/碩士(2013年)

https://doi.org/10.6837/NCNU.2013.00145

摘要

本論文以低雜訊放大器與功率放大器為研究目標。我們設計與實作了一顆低雜訊放大器應用於3.1~10.6 GHz與兩顆應用在K頻帶的功率放大器。研究主題主要分成三部分:
第一部分，我們利用0.18 μm CMOS製程設計實現了一顆低雜訊放大器，應用於3.1~10.6GHz超寬頻系統之高增益低雜訊放大器。在電路架構方面，由兩級電路組成，第一級利用Cascode來提升整體的增益，在輸入端採用RC feedback與Inductor Peaking來達到 wideband matching，而第二級則採用共源極架構，並且用Shunt Peaking技術來達到wideband output matching與低消耗功率。量測結果顯示: 3.1~10.6 GHz頻率下有著最高增益S21為18 dB，輸入返回損耗低於-8.39 dB，輸出返回損耗低於-8.8 dB，雜訊指數2.9~4.6 dB。此電路消耗之功率只有10 mW，非常適合用於低功耗、低雜訊指數的整合系統晶片上。
第二部分為應用在K頻帶之功率放大器，利用0.18 μm CMOS製程技術設計並實現。在電路架構方面，我們設計並實現一級疊接架構功率放大器，使用共源極架構疊接兩個共閘極架構組成疊接的架構。量測結果顯示23.8~27.8GHz下有最高增益為10.7dB，輸入返回損耗低於-10 dB，輸出返回損耗低於-10.3 dB，飽和輸出功率(Psat)為10.2dBm，最大功率附加效率(PAE)為8.71%，而電路整體消耗之功率為68.6mW，且不含test pads之晶片面積則是0.359 mm2。

最後，我們實現一顆應用在K頻帶的高功率附加效率之功率放大器，利用0.18 μm CMOS製程設計實現。在電路架構方面，由兩級電路組成，第一級電路為三層電晶體疊接架構，最後一級則是採用了Wilkinson功率分配器架構以達到輸出功率以及功率附加效率的提升。量測結果顯示此電路的最高增益(S21) 為27.3dB，飽和輸出功率(Psat)為14.42dBm，最大功率附加效率(PAE)為12.13%，而電路整體消耗之功率為151.1mW，且不含test pads之晶片面積則是0.542 mm2。

關鍵字

低雜訊放大器 ； 超寬頻 ； 接收機 ； 功率放大器 ； 輸出飽和功率 ； 功率附加效率 ； K頻帶 ； 疊接 ； Wilkinson功率分配器 ； 發射機

並列摘要

The purpose of this thesis are to research low noise amplifier and power amplifier. We design and implement a low noise amplifier for 3.1~10.6GHz UWB application and two power amplifiers for K-band application. The thesis can be divided into three parts：
The first part is on the design and implement of a high gain low noise amplifier for 3.1~10.6GHz UWB applications in 0.18 μm CMOS technology. In circuit architecture, this circuit consisting of two stages. The cascade-stage structure as first stage to enhanced overall gain. In order to achieve wideband matching, we used the RC feedback and inductor peaking technique. The second stage is implemented with common-source topology, add to the shunt peaking technique to achieve output matching and a lower supply voltage to achieve low power consumption. The measured result shows that high 18 dB gain, S11 below -8.38 dB, S22 below -8.8 dB, flat noise figure of 2.9 ~ 4.6 dB form 3.1 to 10.6 GHz. The result shows of power consuming is only 10mW, that the LNA is suitable for SOC.
The second part is on the design and implement of a power amplifier for K-band applications in 0.18 μm CMOS process. Design and implement a single–stage triple stacked power amplifier, we used a single–stage triple stacked structure which is composed of a common-source input transistor and two common-gate transistors connected in series. The measured result shows that peak gain is 10.7dB, S11 below -10 dB, S22 below -10.3 dB, saturation output power (Psat) is 10.02dBm, max power added efficiency (peak PAE) is 8.71%, total power consumption is 68.6mW and the chip area (excluding test pads) is 0.359mm2.
Finally, we have presented a high PAE power amplifier applications for K band in 0.18 μm CMOS process .In this circuit, we used the triple stacked cascade-stage structure as first stage. The second stage is implemented the Wilkinson power divider/combiner to achieve improving the output power and power added efficiency. The measured results show that the peak gain (S21) is 27.3dB, saturation output power (Psat) is 14.42dBm, max power added efficiency (peak PAE) is 12.13%, total power consumption is 151.1mW and the chip area (excluding test pads) is 0.542mm2. These results indicate that this circuit performs well and is suitable for K-band transmitter systems.

並列關鍵字

low noise amplifier(LNA) ； UWB ； receive ； power amplifier (PA) ； saturation output power(Psat) ； power added efficiency (PAE) ； K-band ； cascade ； Wilkinson power divider/combiner ； transmitter

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