一個長二元BCH碼之IC設計

The IC design of a Long BCH code

張哲濰(Che-Wei Chang)

指導教授 ： 林茂昭

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10160

摘要

由於新一代的快閃記憶體儲存單元越來越小，資料的干擾問題和維持問題卻變的越來越嚴重，也因此降低了記憶體的可靠度。因此錯誤更正碼得研究也越來越重要。

記憶體之錯誤更正碼設計已有一些相關研究。BCH 和 RS 碼是其中兩種最有效的代數碼也是最廣泛使用的方式。在不同之錯誤型態及不同之訊息位元數、檢查位元數等考量之下有多種不同之設計。本論文針對位元已經過擾亂器(interleaver)之處理且錯誤發生率可視為獨立(independent)之情形，考慮BCH(8191,8087,t=8)作編解碼設計。此系統中整合各種先進的架構，其中平行架構可以應用在徵狀(syndrome)區塊及Chien 搜尋區塊減少時脈週期數目，使用修正的歐幾里德的演算法可以解出關鍵方程式，還有分組匹配演算法可以有效降低Chien搜尋區塊乘法器的複雜度，最後將以Xilinx FPGA模擬其效能。

關鍵字

碼 ； 設計 ； 硬體

並列摘要

In new-generation Flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size, and hence it will decrease the reliability of memories. Then, the research of error control coding becomes very important.
There are already some researchs of the hardware design of error correcting code in storage equipments. BCH and RS codes form the core of the most powerful known algebraic codes and are widely used .In this thesis, we focus on the encoder/decoder design of BCH(8191,8087,t=8) code under the condition that the error probabily of all bits are independent due to interleaver operation. We integrate various advanced architecture in our system. The parallel architecture is used to syndrome block and Chien search block in order to reduce system’s clock cycles. Modified Euclidean algorithm is chosen to solve the key equation. And group matching algorithm is to minimize the complexity of the multipliers in Chien search architecture. Finally, the encoder/decoder architecture will be confirmed and simulated by XilinxFPGA.

並列關鍵字

BCH ； code ； IC

參考文獻

[1]Shu Lin, Daniel J. Costello,Jr., Error Control Coding, second ED, Prentice Hall.

[2]Robert H. Morelos-Zaragoza., The art of error correcting coding, Wiley, 2002.

[3]Jyh-Huei Guo and Chin-Liang Wang, “systolic array implementation of Euclid’s algorithm for inversion and division in GF(2^m),” IEEE, 1996.

[4]Yanni Chen , Keshab K. Parhi., “Small Area efficient parallel decoder architecture for long BCH codes,” IEEE Transaction on VLSI systems, vol. 12, No. 5, MAY, 2004.

[5]Arash Reyhani-Masoleh, M. Anwar Hasan, “Low Complexity Bit Parallel Architecture for Polynomial Basis Multiplication over ,” IEEE Transaction on Computers, vol.53, No. 8, AUGUST 2004.