TBLB技術之合成流程

Design Synthesis for TBLB Technology

莊勝傑(Chuang, ShengChieh)

指導教授 ： 陳添福

國立中正大學/工學院/資訊工程學系/碩士(2011年)

摘要

隨著能源越來越缺乏，低功耗的產品已經成為一種趨勢，而降低系統電壓是減少電量消耗最直接且最有的方法之一，但是在低電的環境下，會使得半導體電路的延遲變得更糟，因此如何處於低電壓下達到省電卻又不損失太多效能是一大挑戰。而TBLB 是個可以供給多個電壓的技術，可以達到低功耗又能夠提升電路效能的電路技術，但要使用TBLB在電路上有些限制，因此本篇論文提出了為TBLB設計合成流程，特別是多重供給電壓的合成流程，傳統合成方法只能使用一種電壓模式去合成分析時間，因此對於不同電壓下的時間限制幾乎無法收斂，本篇論文提出了多重供給電壓下合成的方法，可以符合不同電壓下的時間限制，並且使電路達到最佳的功率效能。

關鍵字

合成

並列摘要

With the increasing lack of energy resource, low power has become a tendency. Lowering supply voltage is the most straightforward and effective approach to reduce power consumption. However, under low voltage environment can make the performance of circuits worse. Therefore, how to achieve a target of low power consumption but still keeps the performance under low voltage. The TBLB is a technique with multiple supply voltages and can achieve the low power consumption but also enhance the circuit performance. But using TBLB technique has some restrictions. Therefore, this thesis provides the synthesis flow for TBLB, especially focus on the multiple supply voltage synthesis flow. Traditional synthesis flow can synthesis and analysis just with one power domain. Therefore, traditional synthesis flow is hard to meet the timing constraints of different power domain. This thesis provides the multiple supply voltage synthesis flow and can meet timing constraints of different power domain, and make the circuit to achieve the best power performance.

並列關鍵字

synthesis flow

參考文獻

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