應用於自動測試系統中之高解析度數位時序游標系統電路

High resolution digital timing vernier circuit for Automatic-Test-Equipment (ATE)

王廷元(Ting-Yuan Wang)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電機工程學研究所/博士(2006年)

https://doi.org/10.6342/NTU.2006.01409

摘要

隨著數位積體電路製程的進步以及通訊消費性電子產品之快速發展, 高速數位系統晶片設計變的日趨重要與複雜。隨著許多高速數位化資料傳輸協定之制定, 數位傳輸訊號在時序精確度與解析度上的要求也相對的提高。因此如何設計自動測試系統內部用來產生具有高精準度測試信號的時序游標電路為主要之關鍵。
一個好的時序游標電路其設計重點在於其具有高精確度, 細微的解析度,時序游標長時距調整能力以及低複雜度之電路架構。為了達成長時距調整能力之設計, 本論文第二章中首先提出不受計數位元數目多寡之影響而在高速之固定頻率下操作的可程式化階梯式同步上下數計數器來當做粗刻度時序游標器，以增長時序游標可程式化之時序範圍。此計數器利用反向溢位(Carry Backward)[1]偵測機制以及倒數預測機制[2]來實作同步高速操作。為解決上數/下數計數器所產生計數相位轉向的問題，我們採用線性回饋平移暫存器計數單元(Linear Feedback Shift Register, LFSR)為計數單元，同時加上階梯式模組化架構設計以及溢位信號撰擇機制來完成此一電路設計。
在本文中利用台灣積體電路公司所提供0.35μm CMOS製程之0.65 mm × 0.5mm的面積下完成模擬。同時驗證了利用線性回饋平移暫存器計數單元及反相溢位偵測機制架構的18位元可程式化階梯式同步上下數計數器在525MHz之可行性。
接著為了解決多通道及單一通道多時序需求所造成之大量時序游標電路需求與電路成本問題，在第三章中提出利用自我脈衝寬度控制延遲單元所設計之使用單一迴圈式延遲線的多通道時序游標電路。使得多通道及單通道多時序間各時序信號可利用相同的迴圈延遲電路來產生。如此可以有效的降低不同通道間及不同時序間因電路製程變異而產生的時序不匹配問題，同時可以降低自動測試儀器在設計上因需要使用大量的時序游標電路所增加之電路複雜度及成本問題。本論文中利用一個迴圈式延遲電路來產生三個時序飄移電路。可程式化時距範圍長達1ms。利用32級具有300ps時序延遲之自我脈衝寬度控制延遲單元來實現迴圈延遲線。再利用1/8相位內插電路來完成具有37.5ps解析度之細刻度時序游標。在使用台灣積體電路公司所提供之0.35μm 1P4M CMOS製程下，所設計之晶片面積為 2.33 mm x 2.17 mm。動態非線性特性(dynamic non-linearity, DNL)小於±0.6 最小解析度單位(Least Significant Bit, LSB)。累積非線性特性(Integral non-linearity, INL) 未校正前介於-1倍到7倍最小解析度單位之間。經過方均根誤差校正後之累積非線性特性小於±0.4LSB。多重通道間相位偏移量最大為19ps(方均根值)。時序抖動值為13.7ps(方均根值)。
在完成長時距可程式化時序游標電路及降低電路複雜度及不匹配特性後，第四章中利用N-維游標尺之概念，設計兩種具有超高解析度之N維陣列式延遲鎖定迴圈時序游標電路架構。本文中利用台灣積體電路公司所提供之0.18μm 1P6M CMOS製程來驗證第一型三維陣列式延遲鎖相迴路時序游標電路架構。在此架構之下，可以用較其它時序游標架構為少的延遲單元來達到相同的解析度。同時時序解析度亦可輕易地被設計成所有延遲線數目乘積的倒數倍數。
本文中所設計的延遲鎖相迴路使用133MHz作為參考時脈。利用可以自我切換參考電壓之壓控延遲單元(Reference-voltage switch-controlled delay cell, RVSCDC)使得可程式化延遲線中的任一延遲單元可以切換成具有兩種不同延遲時序的延遲單元。所設計之解析度為15ps，操作頻率範圍介於50MHz到500MHz之間。可程式延遲範圍長達1560ps。所量測之動態非線性特性小於± 0.5LSB。
在大部份的數位時序游標電路系統中, 採用類比充電泵方式的延遲鎖定迴路來產生延遲參考時脈。為進一步簡化設計流程、降低製程變異之影響以及有效降低時序信號之抖動現象，在第五章中我們提出全數位延遲鎖相迴路時序游標電路。同時提出符合全數位式鎖相迴路架構之相位鎖定偵測演算法。在本文中以台灣積體電路公司所提供之0.35μm 1P4M製程參數來模。系統操作於310MHz~450MHz間，中刻度延遲單元之延遲時序為200ps，細刻度解析度為6ps；每一粗刻度延遲時序為32倍細刻度時序延遲。可程式化時序延遲範圍為1.72 ns.
在提出各式改進時序游標電路效能的電路架構後，本文最後於第六章提出利用第三章中所提出之迴圈式延遲線電路來完成用於時序校正之長時距同步時距數位轉換器。在本文中使用台灣積體電路公司提供之0.35μm 1P4M CMOS 製程來實現具有163ps解析度之時距數位轉換器。此一電路可被廣泛的使用在各式量測電路中。而本文中利用此時距數位轉換器電路來量測時序游標電路所產生的時序在量測機台上所產生的非同步誤差並藉以做為校正時序信號之依據，以提高時序電路之精確度。

關鍵字

時序游標產生器 ； 迴圈式延遲線 ； 延遲鎖定迴路陣列 ； 時序數位轉換器 ； 數位延遲鎖定迴路

並列摘要

Owing to the progress of the semiconductor process and quickly development of the communicational consumer electronics, the circuit design of high-speed digital SoC becomes essential and more complexity. Meanwhile, the advanced digital data transmission protocol requires the high precision signal. Thus, designing timing vernier with fine resolution to generate the high precision signal in the automatic-testing-equipment (ATE) is the key issue for furtur testing.
A timing vernier must be designed with high precision, fine resolution, wide programmable range, less complexities and low costs. At the first, we propose a novel design of fast and long constant-time up/down counter using ladder architecture as the coarse delay timing vernier in charpater II. The counter is designed to generate constant carry propagation with any count size. Carry backward[1] and count down prediction mechanism [2]with ladder architecture are adapted to achieve this design. The main problem behind the up/down counter is to recognize that the extra difficulty with an up/down counter (vs. up-only or down-only) when the counter changes direction from counting up to counting down. For dealing with this difficulty, the Linear Feedback Shift Register (LFSR) counting cells[3] and carry selection mechanism is used. When the proposed counter is working as a general counter when counting up or down only. Once the direction changed, the prediction carry signal, carry or borrow, and the data propagation direction is switched in LFSR.
A 18-bit 525MHz carry backward synchronous up/down counter using LFSR counting cells with ladder architecture is presented. This architecture has been fully simulated with TSMC 0.35μm CMOS process. The die size is 0.65mm × 0.5mm
The charpter III of this thesis presents a multiple channel programmable timing vernier with single cyclic delay line using pulse width self controlled delay cells (PWSCDC). The features of highly integrating several timing vernier using single delay line reduces the complexity and cost in ATE. The timing verniers in each channel are propagated from one delay chain. Thus, this structure eliminates the offset of timing verniers between channels which are caused by the circuit mismatches and process variations. This thesis presents the design and measurement results of multiple channel programmable timing verniers using single cyclic delay line for high-speed automatic test equipment (ATE) with 37.5ps resolution and 1ms programmable delay range. There are three timing generators and each one consists of a 19bit 360MHz count-up counter, a 19bit cycle comparator, a zero cycle detector, a control word splitter, and an output selector with an 8x-interpolator. A 32-stage cyclic delay line is constructed by pulse-width self-controlled delay cell (PWSCDC). The proposed timing generator uses the TSMC 0.35 μm 1P4M process with a die size of 2.33 mm x 2.17 mm. The dynamic non-linearity (DNL) is less than ±0.6 LSB (37.5ps). The integral non-linearity (INL) is between –1 LSB and 7 LSB before calibration, and is between±0.4 LSB after root-mean-square value calibration. The multi-channel phase mismatch (MCPM) is 19ps (RMS) and jitter is 13.7ps (RMS).
After achieving the design features of wide programmable delay range and reducing complexities of timeing vernier, we presents a novel timing vernier with ultra-fine resolution using N-dimensional DLL arrays in charpter IV. The proposed architecture is verified with N = 3 using TSMC 0.18um 1P6M process. Fewer delay cells are used to design DLL arrays than other timing vernier circuits. Owing to the N-dimensional structure, the resolution can be designed as multiple result of the number of delay cells in each delay line easily.
The proposed DLL arrays use 133 MHz clock as the reference clock. A reference voltage switching mechanism (RVSM) is used to switch each delay cell between two different reference voltages in the programmable delay line (PDL). Thus, the propagation of each delay cell can be switched in the same delay cell. Proposed timing vernier generates the delay signal with the resolution of 15ps and the operation frequency of PDL is designed from 50 MHz to 500 MHz. The delay range of the timing vernier can be programmed from 0ps to 1560ps. The measurement result of DNL is less than ± 0.5LSB (7.5ps)
In most timing vernier circuits, analog charge pump and current starved delay cells are generally used in the delay locked loop for generating reference timing vernier. In charpter V, we proposed a timing vernier with all digital delay locked loop for simplifying the design with process migration, eliminating the sensitivities with process variation and reducing peak-to-peak jitters. Meanwhile, the locked-detecting mechanism is also presented with jitter analysis. An all digital delay locked loop with 6ps resolutions uses the TSMC 0.35 μm 1P4M process with post simulation verified. The delay range is from 0ps to 1.72ns.
This thesis has proposed several timing vernier architectures to achieve the advanced features for desing timing vernier. In charpter VI of this thesis, a wide range and high-speed time-to-digital converter (TDC) based on a single cyclic delay line is proposed for timing vernier calibration. The TDC is designed to measure the vernier timing and calibrating the generated vernier for higher precision in each timing vernier circuit.
The time-to-digital converter can operate in both single-shot and continuously triggered mode with zero re-arm time, which can be synchronized with a maximum operation frequency of 125MHz. The measurement range of pulse under test (PUT) is from 320ps to 10ms using a 20-bit counter. The resolution can reach 163ps. The DNL is less than ±0.13LS, and the INL is less than ±0.05 LSB after calibration. The TDC has been implemented in 0.35µm 1P4M process with chip area 1.48mm × 1.41mm.

並列關鍵字

Time-to-Digital Converter ； TDC ； Timing Vernier ； DLL arrays ； Digital Delay Locked Loop ； DDLL

參考文獻

[28] 陳怡仁, "用於自動測試儀器的具數位控制量化誤差延遲鎖相迴路之時序產生器設計," 國立台灣大學電子工程學研究所碩士論文, June 2004.

[38] 陳佳煒, "使用三維差分時序之微微秒解析度精確延遲產生電路," 國立台灣大學電子工程學研究所碩士論文, June 2004.

[1] P. Larsson and J. R. Yuan, "Novel Carry Propagation in High-Speed Synchronous Counters and Dividers," Electronics Letters, vol. 29, pp. 1457-1458, Aug. 1993.

[2] H.-H. Chang and J.-C. Wu, "A 723-MHz 17.2-mW CMOS programmable counter," IEEE J. of Solid-State Circuits, vol. 33, pp. 1572-1575, October 1998.

[3] M. R. Stan, A. F. Tenca, and M. D. Ercegovac, "Long and Fast Up/Down Counter," IEEE Trans. on Computers, vol. 47, no. 7, pp. 722-735, July 1998.