用於自動測試儀器的具數位控制量化誤差延遲鎖相迴路之時序產生器設計

The design of the timing generator with digital control quantized delay locked loop in automatic test equipment

陳怡仁(Yi-Zen Chen)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.01323

摘要

摘要

在本論文中，介紹了好幾種架構的時序產生器和延遲鎖相迴路。在時序產生器的設計中，很難同時達到高解析度，程式化延遲範圍大，和小的初始延遲。我們提出一種混合式時序產生器架構。在延遲鎖相迴路的設計中，數位式架構比起傳統類比式的優點是系統的穩定度較不易受到製程變異的影響，而且較能達到大範圍的延遲時間。
而我們提出一種具鎖定偵測演算法的數位式鎖相迴路，以台積電0.35微米CMOS製程實現微調時序產生器。
在以台積電0.25微米CMOS標準單元製程實現粗級時脈產生器中，它的架構以計數器陣列方式實現。我們使用進位預測機制來增加它的操作頻率。操作頻率並不會因計數位元增加而減少。

關鍵字

數位控制量化誤差延遲鎖相迴路

並列摘要

Abstract

In this thesis, several architectures of timing generator and delay locked loop are introduced. In timing generator design, it is hard to fulfill high resolution, wide programmable delay range and intrinsic delay at the same time. We proposed a mixed architecture of timing generator. In delay locked loop design, the advantage of the digital architecture over traditional analog one are that system stability is independent on process variation and wide tunable delay range is possible.
And a new digital delay locked loop with lock-detecting algorithm is presented to realize a fine timing generator by TSMC 0.35um CMOS process.
In coarse timing generator implemented with TSMC 0.25um CMOS standard cell process, its architecture is realized by counter array. We using carry prediction mechanism to increase its operation frequency. The operation frequency has nothing to do with the bit count of the counter.

並列關鍵字

digital control quantized delay locked loop

參考文獻

［2］ Christopher W. Branson, “Integrated Pin Electronics for a VLSI test system,” IEEE Trans. on Industrial Electronics, Vol.36 ,No.2, MAY. 1989

［3］ James A.Gasbarro and Mark A.Horowitz, “Integrated Pin Electronic for VLSI functional testers,” IEEE J. Solid-State Circuit , Vol.24, No.2,pp.331~337, Apr. 1989.

［4］ Jim Chapman, “High performance CMOS based VLSI testers:timing control and compensation,” IEEE International Test Conference,pp.59~67,1992

［6］ Tai-lchi Otsuji and Naoaki Narumi, ”A 10-ps resolution , process-Insensitive timing generator IC”, IEEE J. Solid-State Circuits , vol.24,No.5,OCT.1989

［7］ Christopher W. Branson, “Integrated pin electronics for a VLSI test system,” IEEE Trans. on Industrial Electronics, Vol.36, No.2 pp.185-191,MAY. 1989