背景消除供應電壓雜訊的數位鎖相迴路與注入鎖定時脈倍頻器

Digital Phase-Locked Loop with Background Supply Noise Cancellation and Injection-Locked Clock Multiplier

曾彥閔(Yen-Min Tseng)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202001647

摘要

這篇論文的主題主要分為兩個部分，第一部分實現了一個具有背景消除供應電壓雜訊的數位鎖相迴路。藉由使用一個數位穩壓器以及全數位電壓源雜訊消除方法，此數位鎖相迴路可以承受峰對峰值為240mV的供應電壓源雜訊。此數位鎖相迴路使用台積電40奈米製程，面積為0.0195mm2 而功耗在1.1V的供應電壓下為7.23mW。數位振盪器量測到最小的電壓源雜訊敏感度低於0.0261[%-fDCO/%-VDD]。在供應電壓源注入峰對峰值為240mV，頻率為100kHz的弦波雜訊時，量測到的方均根抖動量從原本的56.38ps降低至15.72ps。
第二部分實現了一個具有注入強度校正的注入鎖定時脈倍頻器。通過控制電荷泵電流，可以使用注入強度校正器來校準注入鎖定時脈倍頻器的注入強度。此注入鎖定時脈倍頻器使用台積電40奈米製程，面積為0.0253mm2 而功耗在1V的供應電壓下為4.28mW。參考頻率為150MHz，輸出頻率為2.4GHz以及除數為16。相位噪聲積分範圍從1kHz到100MHz所量測到的方均根抖動量為878fs。

關鍵字

數位鎖相迴路 ； 電壓雜訊消除 ； 注入鎖定時脈倍頻器 ； 注入強度校正

並列摘要

This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply noise cancellation. By using a digital low-dropout regulator and a supply noise cancellation controller, this DPLL can tolerate a supply noise of 240mVPP. The DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0195mm2 and the total power consumption is 7.23mW from a supply of 1.1V. The minimum measured supply voltage sensitivity of the digital-controlled oscillator is less than 0.0261 [%-fDCO/%-VDD]. With a 100kHz, 240mVPP sinusoidal supply noise, the measured rms jitter is reduced from 56.38ps to 15.72ps.
The second part implements an injection-locked clock multiplier (ILCM) with injection strength calibration. By controlling the charge pump currents, an injection strength calibrator is used to calibrate the injection strength of the ILCM. This ILCM is fabricated in 40-nm CMOS technology. Its active area is 0.0253mm2. The power consumption of the ILCM is 4.28mW from a supply of 1V. The reference frequency is 150MHz and the output frequency is 2.4GHz with a divider ratio of 16. The measured rms jitter integrated the phase noise from 1kHz to 100MHz is 878fs.

並列關鍵字

digital phase-locked loop ； supply noise cancellation ； injection-locked clock multiplier ； injection strength calibration

參考文獻

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