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  • 學位論文

高壓N型金氧半電晶體對於源極與基極佈局參數對靜電放電特性的研究

Study of Source and Body Contacts Layout Design to High Voltage NMOS ESD Protection Devices

指導教授 : 陳秋麟

摘要


在本研究中,分析了高壓N型金氧半電晶體元件在靜電放電發生及元件在高電壓導通時的電流與電壓特性。靜電放電防護的旁通電晶體在應用於大尺寸的通道寬度時,必須以多指狀結構(multi-finger)來佈局(Layout),以提高旁通電晶體的佈局效益。然而由於N型金氧半電晶體具有明顯的驟回崩潰 (Snapback Breakdown) 特性,以及多指狀結構佈局上每一根相對於基體 (Substrate) 中N型橫向寄生雙載子電晶體與連接至基極的等效電阻之不同,在靜電放電衝擊下造成多指狀結構N型金氧半電晶體,不會同時導通來旁通此一靜電放電電流,卻是集中於部分指狀N型金氧半電晶體。此N型金氧半電晶體不均勻導通的現象使得靜電放電耐受度無法隨著增加元件通道寬度尺寸增大而線性增加,造成靜電放電防護電路設計的困難。 此篇論文主旨在改變源極與基極的佈局參數在多指狀結構N型金氧半電晶體。並據以找出高壓元件靜電放電最佳化的佈局規則。並增強其靜電放電耐受度。因此我們設計了不同佈局參數的元件,再利用傳輸線觸波產生器量測觀察其靜電放電均勻度。本研究實驗及分析的結果,可以作為未來高壓元件在更深入研究與設計時的重要依據。

並列摘要


This study analyzes the characteristic of ESD (electro-static-discharge) of high voltage NMOS (N-type metal oxide semiconductor) transistor current and voltage when NMOS is turned-on in high voltage. When the width of bypass MOS in the ESD protection circuit has to layout in the multi-finger type so as to decrease the layout area cost, in the mean while, due to the snapback breakdown of NMOS and the resistance connecting the base of the parasitic lateral bipolar transistor in the substrate is individually different. These sub-multi-finger NMOS’can not be turned on simultaneously. The ESD current is passed in few MOS’. The uniform turn-on of NMOS results in the endurance of ESD can increase as the width of protection device is increased. In this condition, it is more difficult to design an ESD protection circuit. This thesis is trying to change the layout parameters of source and bulk of a multi-finger NMOS so as to find out optimal layout rules of a high voltage ESD protection device. Different layout parameter of NMOS’are tested. The uniformity of ESD devices are measured by transmission pulse generator. The results of this study can provide evidences for further study of high voltage ESD device.

參考文獻


[1] S. Voldman, ESD: Circuits and Devices, John Wiley & Sons, Ltd. England 2004.
[2] K.-H. Oh, C. Duvvury, K. Banerjee, and R. W. Dutton, Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors” IEEE Trans. Electron Devices, vol. 49, pp. 2171-2182, Dec 2002
[3] K.-H. Oh,C. Duvvury, K. Banerjee, and R. W. Dutton, “Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors” IEEE Trans. Electron Devices, vol. 49, pp. 2171-2182, Dec. 2002
[4] T.-Y. Chen and M.-D.Ker,“ Investigation of the gate-driven effectand substrate-triggered effect on ESD robustness of CMOS devices,” IEEE Trans. Device and Material Reliability, vol. 1, pp. 190-203, Dec. 2001.
[5] T. Polgreen and A. Chatterjee, “Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow,” IEEE Trans. Electron Devices, vol. 39, pp. 379–388, Feb. 1992.

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