鍺之金氧半電容製備與特性分析及射頻開關之模擬

Fabrication and Characterization of Ge MISCAPs and Simulation of RF Switches

張達智(Da-Zhi Chang)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201701821

摘要

隨著摩爾定律半導體元件尺寸不斷地縮小，增加單位面積的電晶體數使得晶片能實現更複雜的又快速的運算。以矽作為元件通道的金氧半場效電晶體逐漸達到微縮的極限，必須更換具有較高載子遷移率的材料作為元件的通道。其中同樣為四族元素的鍺有高的載子遷移率並且與其製程與目前的矽互補金氧半製程匹配，因此被看好為取代矽通道的材料。本篇論文中，我們製備了鍺金氧半電容並將其特性分析。
首先我們使用快速熱氧化法於鍺樣品表面成長氧化鍺，並使用原子層沉積來形成高介電系數的三氧化二鋁，接著以熱蒸鍍形成鋁電極。在此製程中，氧化鋁鍺形成於鍺的介面，並具有低至1E11 cm-2eV-1的介面缺陷密度。另外我們製備了具有此氧化鋁鍺介面的p型電晶體，萃取出其載子遷移率。其載子遷移率之峰值為277 cm2/V-s。因為較低的庫倫散射，其載子遷移率較介面為氧化鍺的電晶體高。
接著為功函數金屬氮化鈦於鍺閘極堆疊的探討。藉由鍵鍍氮化鈦時通入不同流量的氮氣以改變氮化鈦中的氮含量。並藉由製備鍺金氧半電容萃取出氮化鈦之功函數，數值介於4.54 eV到4.74 eV之間。在以氮化鈦為閘極的鍺金氧半電容上再覆蓋上鉑，能使得電容磁遲滯效應低至70mV，而以低溫電導方法萃取出介面缺陷密度約為1E11 cm-2eV-1。
最後一個部分為射頻開關於絕緣層上覆矽基板之TCAD模擬。絕緣層上覆矽基板之等效電阻率反映了射頻訊號於基板損失之多寡。模擬結果顯示握持晶圓之摻雜濃度越低，絕緣層上覆矽基板之等效電阻率越高。我們並提出了一種絕緣層上覆矽基板結構，在基板之絕緣層與握持晶圓介面上加入溝槽的結構，藉此提高(27.5%)基板之等效電阻率。射頻開關中的電晶體元件於此基板有較低的Off-state電容值。

關鍵字

鍺金氧半電容 ； 氧化鋁鍺 ； 射頻開關 ； 絕緣層上覆矽基板 ； 等效電阻率

並列摘要

As Si CMOS industry confronts the fundamental limitation for the further scaling to fit the Moore’s Law, Ge is a promising channel material for advanced technology nodes to replace Si. In this thesis, properties of Ge gate stacks are investigated.
For the first part, Ge surface was well passivated by GeOx grown by RTO and Al2O3 deposited by ALD with the inclusion of Al forming the AlGeO interfacial layer with low Dit (~1E11 cm-2eV-1) near the midgap. The reduction of CET was achieved by lower RTO temperature and lower number of cycle of ALD. The Dit of MISCAPs could be reduced by PMA. The Ge pFETs with the AlGeO interfacial layer shows the peak mobility of 277 cm2/V-s.
For the second part, the Ge MISCAPs with workfunction metal TiN were fabricated. The TiN was deposited by sputtering. The workfunction of TiN is extracted as 4.54 eV, 4.64 eV and 4.74 eV for different sputtering conditions. Low hysteresis (70mV) of the Ge MISCAPs with additional Pt capping layer and low Dit (~1E11 cm-2eV-1) near the midgap for the interface are demonstrated.
For the last part, which focus on the RF switches on SOI substrate, the effective resistivity of SOI substrates is characterized by TCAD simulation. A proposed SOI structure with textures at the BOX/Si handle substrate interface demonstrated a higher effective resistivity (27.5% improvement) as compared to the conventional ones. The transistor on the proposed SOI substrate shows the lower off state capacitance.

並列關鍵字

Ge MISCAPs ； AlGeO ； RF switch ； SOI substrate ； effective resistivity

參考文獻

1.3 References

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2.6 References

[1] S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y.Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara, and N.Sugiyama,