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鍺與三五族鰭式電晶體之共用高介電/金屬閘極製程開發與模擬分析優化研究

Development of Ge/IIIV Fin Field-Effect Transistor Common Gate Process and Its Numerical Simulations

摘要


由於積體電路技術的蓬勃發展,現今電晶體已趨向超高密度之製造與元件尺寸微縮至奈米化方向發展,在結構上具高深寬比(Aspect Ratio) 之特性,而線寬更朝向深次奈米(Deep ub-nanometer) 邁進。因此,於現今半導體元件製程中,高品質且薄之薄膜沉積技術已被視為一極重要之研究課題。從薄膜的厚度、鍵結結構及其緻密度與半導體表面之附著特性將對其電子元件的電性及效能乃至到可靠度都有其極大之影響。本研究主要是利用熱原子層(Thermal Atomic Layer Deposition, TALD) 沉積系統於鍺(Ge) 基板及砷化鎵銦(InGaAs) 材料上, 探討其製程參數最佳化及3D 鰭式電晶體(FinFET) 之製作與電性分析, 並利用熱流場之機制與CFD(Computational Fluid Dynamics) 模擬等技術來探討薄膜之形成及品質改善,以預期能精確控制薄膜厚度與結構而應用於鍺(Ge) 及砷化鎵 (InGaAs) 鰭式電晶體(FinFET) 元件之製作及電性最佳化,以應用於半導體產業製程。

並列摘要


For the progression in IC manufacturing of the nanometer regime, transistor devices have the trend of high density capacity with nanometer-size volume; their structure presents characteristics of high aspect ratio and 10 nanometer-width wire. Therefore thin film deposition technology has become an important research topic in the field of semi-conductor industry. Film thickness, film structure and surface structure are relevant to influence the performance and electricity of the devices. This project aims to study the manufacturing process of thermal atomic layer deposition (TALD) and analyze its thermal physical mechanism. Moreover, experiment and the technique of computational fluid dynamics (CFD) will be used to investigate the film's forming and deposition rate for controlling precisely its thickness and structure. This paper is one year period. Firstly, the design of the TALD system model will be analyzed, then CFD will be used to simulate the optimal parameters, such as gas flow, thermal, pressure and concentration fields, in manufacturing process to assist the fabrications of oxide-semiconductor and its devices, and improve their characteristics. Besides, the experiment in this project will apply the ADL process to grow films on Ge and GaAs substrates with 3D transistors of high electric performance.

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