次波長光學微影效應對超大型積體電路之元件與電路特性影響之分析

當積體電路之線寬隨著摩爾定律縮小到次波長等級，非理想之光學效應，例如:光學鄰近效應、像差、繞射等，變得愈來愈嚴重，在半導體微影製程中，即使利用解析度增強技術，這些效應或變異亦將造成矽晶圓上成像之圖形失真。這些非理想的圖形將影響製造出來之元件電氣特性，如驅動電流、漏電流、臨界電壓。現今之電晶體模型無法處理非長方形的閘極形狀。為了分析微影後(post-litho)之電路特性，非長方形電晶體模型(non-rectangular model)是不可或缺的。在本論文裡，我們探討各種非長方形電晶體之模型方法。我們運用元件模擬軟體來檢視窄寬長效應(Narrow width effects)對元件特性的影響，並且驗證等效閘極通道長度(Equivalent gate length)模型方法的精確度。為了增進漏電流分析之準確度，我們提出一個位置相依之權重函數(location-dependent weighting function)來考慮窄寬長效應造成之漏電流變異。最後，我們建立一個結合光學效應與電路特性之模擬流程，運用此模擬流程，我們探討光學鄰近修正(OPC)設定，如修正次數與切割長度，對靜態隨機存取記憶體(6T-SRAM)微影後之電路特性的影響。

關鍵字

微影製程；光學鄰近修正；非長方形電晶體；窄寬長效應；位置相依之權重函數

並列摘要

As the critical dimension of integrated circuits reduces to sub-wavelength following the path of “Moore’s law”, non-ideal optical effects, such as optical proximity effects, aberration, and optical diffraction, become more serious. Those effects or variations would result in wafer pattern distortions even applying resolution enhancement techniques (RETs). The non-ideal patterning would impact the electrical characteristics of manufactured devices, including drive current (Ion), leakage current (Ioff), and threshold voltage (Vth). Today’s compact transistor models can not handle the non-rectangular gate shape. The model of non-rectangular transistor is indispensable for post-litho circuit simulation. In this thesis, different non-rectangular transistor modeling approaches are discussed. TCAD device simulator is utilized to examine the impacts of narrow width effects on device characteristics. The accuracy of equivalent gate length (EGL) modeling approach is verified based on device simulations. To improve the accuracy for leakage current analysis, a location-dependent weighting function is proposed to take into account the leakage current variation due to narrow width effects. Finally, a post-litho simulation flow that combines the lithographic effects and circuit performance is built. The impacts of OPC settings, including number of corrections and segmentation length, on post-litho circuit performance is discussed based on a 6T-SRAM cell.

並列關鍵字

Lithography ； Optical Proximity Correction ； Non-rectangular transistor ； Narrow width effects ； location-dependent weighting function

參考文獻

[1] G. E. Moore, Cramming More Components onto Integrated Circuits, Electronics, pp. 114-117, 1965

[2] E. Seevinck, F. List, and J. Lohstroh, Static-Noise Margin Analysis of MOS SRAM Cells, IEEE J. Solid-State Circuits, vol. SC-22, pp.748–754, 1987

[4] J. R. Sheats and B. W. Smith, Microlithography: science and technology, MARCEL DEKKER, 1998

[5] A. Balasinski, H. Gangala, V. Axelrad, and V. Boksha, A Novel Approach to Simulate the Effect of Optical Proximity on MOSFET Parametric Yield, in Electron Devices Meeting, IEDM Technical Digest, pp.913-916, 1999

[6] A. K. K. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE, 2001

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次波長光學微影效應對超大型積體電路之元件與電路特性影響之分析

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