本論文提出五種組合型電路與掃描鏈短路型錯誤的模組,這種短路型錯誤的一端是屬於組合型電路,而另一端屬於掃描鏈。根據實驗結果顯示,此種組合型電路與掃描鏈短路型錯誤有別於所有已知的錯誤,而是會受到掃描進入的影響。此篇論文提出一個精準的診斷演算法診斷組合型電路與掃描鏈短路型錯誤。另外,此篇論文亦提出一個鄰近電路配對擷取演算法,此演算法可以利用電路的實體設計佈局快速找出可能發生短路的相鄰電路組。在ISCAS’89基準電路的實驗顯示,平均而言對組合型電路與掃描鏈短路型錯誤的診斷結果準確率為最多三組鄰近電路配對。當錯誤資料相當有限時,本論文提出的技術仍然十分有效。
This thesis proposes five logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike any existing fault, depend on the previous scan inputs as well as primary inputs. An accurate diagnosis technique is presented to locate logic-chain bridging faults. In addition, a bridging pair extraction algorithm is proposed to quickly extract bridging net pairs from the layout. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of three bridging pairs. The technique is still applicable when only ten failing patterns are recorded on the tester.