透過您的圖書館登入
IP:3.21.52.82
  • 學位論文

閘極金屬厚度對超薄氧化層金氧半元件雙態特性之影響

Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide

指導教授 : 胡振國

摘要


本篇論文探討對於超薄氧化層金氧半電容元件,閘極金屬之厚度對於元件的電流電壓以及電容電壓特性之影響。近幾年來,嵌入式隨機存取記憶體對於半導體產業越來越重要,在許多範疇,如系統晶片、特殊應用積體電路等等都大量使用嵌入式隨機存取記憶體。在本研究記憶體元件的圖型由相連的長帶與方型連接點構成,希望能配合超薄閘極金屬產生更明顯的閘極電阻變化。操作方法有兩種,電流模式與電容模式。我們首先討論電流模式,在此模式下,輸出電流信號非傳統隨機存取記憶體之大小差異,而是分成正負電流,此處分別標示為狀態‘1’與狀態‘-1’。其信號維持時間常數約為210ms,符合於2013年公布的ITRS標準,並且可承受至少一百萬次寫入操作。接下來是電容模式之討論。在此模式下,電容磁滯現象的程度代表了元件的優劣,磁滯現象越明顯記憶體特性越好,我們將電容電壓來回掃描之電容差異設定為記憶指標。而此元件的電容磁滯現象,或可稱平能帶電壓位移與電壓大小以及偏壓維持時間有相當密切關係,但這兩項參數會相互消長,其中還需要取捨。電容操作模式的結果展示了以此金氧半電容結構進一步發展成電晶體記憶體時的潛力。綜合而言,本篇論文中所討論的揮發式隨機存取記憶體元件具有以下優點:結構簡單易製做、元件尺寸小、與CMOS製程相容、低功耗。

並列摘要


In this work, we study the effect of the thickness of gate metal on the characteristics of Metal-Oxide-Semiconductor capacitor (MOSCAP) device with ultrathin oxide layer. The embedded Dynamic Random Access Memory (eDRAM) becomes more and more important in semiconductor industry with application of System on Chip (SoC) and Application Specific Integrated Circuit (ASIC). The pattern of the device is a long strap connected to a square contact pad in this work, which is designed for higher gate resistance with ultrathin gate metal. The device has two operation modes, i.e., current mode and capacitance mode. For current mode operation, the device exhibits 2-state characteristic with opposite readout current sign, which we define as ‘1’-state and ‘-1’-state. The device has retention time constant of about 210ms, which matches the specification of ITRS. And it has endurance of at last one million cycle of write operation. For capacitance mode operation, the device shows CV hysteresis with thinner gate metal and thin oxide layer. The level of CV hysteresis is sensitive to sweeping range and stress holding time. And the two factors are tradeoff for high sensitivity. The capacitance 2-state characteristic of the MOSCAP device has the potential to evolve into transistor memory. The device discussed in this work has advantage of simple structure, smaller feature size, CMOS process compatible, and low operation power consumption.

參考文獻


[2] J. Barth, W. R. Reohr, P. Parries, G. Fredeman, J. Golz, S. E. Schuster, et al., "A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier," IEEE Journal of Solid-State Circuits, vol. 43, pp. 86-95, 2008.
[3] W. Kong, P. C. Parries, G. Wang, and S. S. Iyer, "Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation," in IEEE International Test Conference (ITC 2008), pp. 1-7, 2008.
[4] T. Hamamoto, S. Sugiura, and S. Sawada, "On the retention time distribution of dynamic random access memory (DRAM)," IEEE Transactions Electron Devices, vol. 45, , pp. 1300-1309 1998.
[6] H. Tanaka, M. Kido, K. Yahashi, et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," in Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15, 2007.
[8] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, "Failure mechanisms of flash cell in program/erase cycling," in IEEE International Electron Devices Meeting (IEDM '94) Technical Digest, pp. 291-294, 1994.

延伸閱讀