定電壓應力操作對超薄氧化層金氧半電容元件之電特性影響分析及其元件應用

Effect of Constant Voltage Stress Treatments on the Electrical Characterization and Device Application of MOS Capacitor with Ultra-Thin Oxide

陳姿妤(Tzu-Yu Chen)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2014年)

https://doi.org/10.6342/NTU.2014.11077

摘要

非理想因子一直存在於電子元件之中，並隨著元件的微縮，影響隨之加劇。
金氧半元件中橫向的不均勻性（平行於通道或是閘極氧化層方向）為其中一非理
想因子。在眾多橫向的不均勻現象之中，邊際電場效應（fringing field effect）為電場分布的不均勻。實驗結果顯示，不論照光與否，超薄閘極氧化層P 型金氧半電容（p-MOSCAP）之反轉區電流皆主受控於電洞電流。此電洞電流的大小受到存在於二氧化矽�矽介面電洞的等效蕭基能障高度（effective Schottky barrier height）所支配，並被邊際電場效應所強化。換句話說，元件周長區域電洞的等效蕭基能障大小調控元件的反轉區電流。在本論文之中，探討定電壓應力操作對此P 型金氧半電容之電特性所造成的影響及其可能的應用。負偏壓或正偏壓的定電壓應力（constant voltage stress）操作，為一將電子捕陷於二氧化矽氧化層中或釋放的方法，並藉由此被捕陷或釋放的電子調控電洞的等效蕭基能障高度。當元件施加適當的負偏壓與正偏壓的定電壓應力操作後，可得雙態的反轉區電流以及電容。在施加負偏壓的定電壓應力操作後，由於有些許的電子被捕陷於二氧化矽氧化層之中，而屏蔽反轉區電子的生成，反轉區電子數量驟降，降低二氧化矽氧化層的壓降，而增大電洞的等效蕭基能障高度。此外，二氧化矽氧化層電壓的下降則會增加落在矽基板上的電壓，使得矽基板的空乏區變大。因此，可觀察到降低的反轉區電流與電容。值得注意的是，此些許被捕陷於二氧化矽氧化層中的電子，會使反轉區電容的頻率響應消失。在另一方面，正偏壓的定電壓應力操作則可使原本被捕陷於二氧化矽氧化層內的電子被釋放，使反轉區的電流與電容上升回復到原始狀態。此雙態的反轉區電流以及電容現象提供了可能的應用於記憶體元件之中。最後，將反轉區電流隨負偏壓的定電壓應力操作而下降的特性應用於可見光偵測器之上。由於被捕陷於二氧化矽氧化層中的電子可大幅降低元件的暗電流，此光偵測器的光敏感度（photo sensitivity）可以被有效的改善。此方法同時提供了一個可能的應用於改善可見光偵測器的光敏感度之上。

關鍵字

金氧半電容 ； 超薄閘極氧化層 ； 不均勻性 ； 邊際電場效應 ； 蕭基能障 ； 定電壓應力操作 ； 金氧半光偵測器

並列摘要

Non-ideal factors always exist in electrical devices and the factors become significant in downscaling devices. Lateral non-uniformity, along the channel or in a direction paralleling to dielectric layers, is one of the non-ideal factors in the MOS devices. Among various phenomena of the lateral non-uniformity, fringing field effect is the significant one in the electrical field distribution. The experimental results indicate that the hole current dominates the inversion gate current of a p-MOSCAP with an ultra-thin SiO2 layer, both under the dark and illumination conditions. The value of the hole current is modulated by the effective Schottky barrier height of hole appearing at SiO2/Si interface and is further enhanced by the fringing field effect. In other words, the value of the effective Schottky barrier height of hole in the device-edge region modulates the value of the inversion gate current. In this dissertation, the effects of the constant voltage stress treatments on the electrical characterization of the p MOSCAP are investigated. Besides, their potential application is also proposed. A negative/positive constant voltage stress treatment is utilized as a method to trap/de trap electrons in SiO2, and further modulates the value of the effective Schottky barrier height. Two-state inversion gate current and inversion capacitance are achieved after applying suitable treatments. After applying a negative constant voltage stress treatment onto a p-MOSCAP, a few electrons are trapped in IV SiO2. These trapped electrons screen the inversion electrons at Si surface, reduce the voltage drop of SiO2, and further increase the effective Schottky barrier height of hole. Besides, the reduced SiO2 voltage enlarges the Si surface band bending and broadens the depletion width. Therefore, evident decrements in the inversion gate current and inversion capacitance are observed. In particular, due to few inversion electrons atSi surface, the response of the inversion capacitances to AC frequencies disappears. In contrast, the electrons in SiO2 are de-trapped after applying a positive constant voltage stress treatment onto the device. Then, the reduced inversion gate current and the reduced inversion capacitance increase and revert to their original statuses. The two-state inversion gate current and inversion capacitance phenomena provide a potential application in memory devices. Subsequently, the negative constant voltage stress treatment is also applied onto a visible-light MOS photodetector. A few electrons are trapped in SiO2 of the device, and greatly reduce the inversion dark current. Due to the evident decrement in the inversion dark current, the photo sensitivity of the photodetector is enhanced. It provides a potential application in the enhancement of the photo sensitivity of a visible-light MOS photodetector.

並列關鍵字

MOSCAP ； ultra-thin SiO2 ； non-uniformity ； fringing field effect ； Schottky barrier ； constant voltage stress ； MOS photodetector

參考文獻

[1] Y. Nakajima, T. Toda, T. Hanajiri, T. Toyabe, and T. Sugano, “In-depth profiling of electron trap states in silicon-on-insulator layers and local mechanical stress near the silicon-on-insulator/buried oxide interface in separation-by-implanted-oxygen wafers,” Journal of Applied Physics, vol. 108, pp. 124505-124505-5, 2010.

[2] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, “Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm,” in Electron Devices Meeting, 2002. IEDM '02. International, 2002, pp. 47-50.

[3] J. Koga, S. Takagi, and A. Toriumi, “Influences of buried-oxide interface on inversion-layer mobility in ultra-thin SOI MOSFETs,” Electron Devices, IEEE Transactions on, vol. 49, pp. 1042-1048, 2002.

[4] J.-C. Tseng and J.-G. Hwu, “Lateral Nonuniformity Effects of Border Traps on the Characteristics of Metal–Oxide–Semiconductor Field-Effect Transistors Subjected to High-Field Stresses,” Electron Devices, IEEE Transactions on, vol. 55, pp. 1366-1372, 2008.

[5] W. K. Chim and P. S. Lim, “Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (< 5 nm) nitrided oxides,” Journal of Applied Physics, vol. 91, pp. 1304-1313, 2002.