本論文的目的在實現電容式感測器之佈局,並且比較佈局前後之性能變化,文中介紹佈局之技巧與通則以及電阻及電容的佈局方式,並以隔離環阻隔寄生電容效應,對差動電路以對稱性消除雜訊,最後模擬佈局後電容改變量和電壓輸出之關係,此電路佈局之解析度可達 法拉等級。 而本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC)所提供的台灣積體電路(TSMC)0.35μm Mixed-Signal 2P4M Polycide 3.3/5V的製程,並使用Synopsys 公司所出的Hspice電路模擬軟體進行模擬以及思源公司的laker軟體進行佈線。
The purpose of this dissertation is to realize the design and layout of capacitive sensing circuit, and in this case to compare the differences before and after layout. In this dissertation presents the skills and principles of layout, and also the method of designing resistance and capacitor. Furthermore, using guard ring to shield noise effect, and using symmetry to eliminate the noise of differential circuit, at the end of this dissertation is to simulate the relations between variety of capacity as well as output voltage after layout. The circuit after layout has the best resolution which is up to 1fF. This dissertation is applying 0.35μm Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSCM which is provided by NSC Chip Implementation Center. Finally, using Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout.