應用系統層級設計方法在SoC平臺架構之探討

Exploration of SoC Platform Architectures Using the System-Level Design Methodology

陳振隆(Zhen-Lung Chen)

指導教授 ： 王勝德

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10370

摘要

隨著IC製程的進步，今日已可以將上億個電晶體置入到一個晶片，也使得今日系統晶片的設計日趨複雜。系統層級的設計方法使得系統開發人員可以提高設計的抽象層次，在設計階段能快速的進行實驗，收集數據加以分析與改良系統架構，進而降低系統單晶片開發的複雜度。本篇論文使用了CoWare的系統層級開發工具ConvergenSC，並採用SystemC硬體描述語言。在這篇論文中以交易層級模組化方法設計各個硬體元件建立抽象模型，並使用這些工具在高抽象層次建構三個交易層級的虛擬原型系統架構，藉由模擬出來的數據分析各個系統架構的效能，並加以探討在各個系統架構的優劣點。

關鍵字

系統層級 ； 交易層級模組化 ； 系統單晶片 ； 電子系統級 ； 架構探討

並列摘要

With the improvement of IC manufacturing technologies, hundred millions of transistors could be put into one chip, and this also leads the system chip design to a more and more complex situation. The design methodology on the system level helps system developers advance the abstraction level of design, validate and verify the design at early stage, collect and analyze data and improve system structures so as to reduce the development complexity of a system-on-chip. The systemC hardware description language and ConvergenSC, a development tool on the system level of CoWare Inc., are adopted in our work. In this thesis, the methodology of transaction-level modeling is used to design hardware components and build abstract models, and the ConvergenSC tool is used to build three transaction-level virtual prototypes of system-on-a-chip platforms. We can analyze the efficiency of each system platform through the simulated data, and evaluate the strength and weakness of system architectures.

並列關鍵字

System-level ； TLM ； SoC ； ESL ； Architecture Exploration

參考文獻

[2]P. Schaumont, and I. Verbauwhede, “a component-based design environment for esl design,” IEEE Design & Test, 2006.

platform-based design,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 1523-1543, Dec. 2000.

[6]T. Hollstein, J. Becker, and A. Kirschbaum, HiPART: A New Hierarchical Semi-Interactive HW/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems, 6th International Workshop on Hardware/Software Codesign, 1998.

[8]E. D. Lagnese, and D. E. Thomas , “Architectural Partitioning for System Level Design,” Design Automation, 1989. 26th Conference on, 1989.

[10]A. P. Su, and R. Chen, “Applying ESL in A Dual-Core SoC Platform Designing,” International SOC Conference, 2006 IEEE, 2006.