基於 RISC-V 指令集架構的 SoC 之設計與實作

The design and implementation of an SoC based on the RISC-V Instruction Set Architecture

巫謹佑(Jin-You Wu)

指導教授 ： 蔡淳仁

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2019年)

摘要

本論文的目的是設計並實現一個基於RISC-V指令集架構(ISA)的系統單晶片(SoC)。RISC-V是一個基於精簡指令集(RISC)原則的開源指令集架構，與大多數的RISC ISA相比，RISC-V指令集可以自由地用於任何目的，允許任何人設計、製造和銷售RISC-V晶片和軟體。
近年來，在物聯網繁榮發展的促使下以及商業化RISC指令集的授權金與專利等問題，RISC-V迅速崛起，因應物聯網場景需求碎片化，對低功耗、低成本、客製化的需求高，而這些剛好都是RISC-V指令集有的特性。
因此，在本研究中，我們將設計一個支援RV32IM的RISC-V處理器。在設計與實現完成後，我們會在全系統模擬的環境下通過RISC-V官方所提供的測試程式來驗證我們處理器是否符合指令集架構定義以及使用標準的Dhrystone benchmark來評估其性能(DMIPS/MHz)。此外，我們也會在Xilinx FPGA KC-705開發版上進行全系統驗證，確認我們所開發的RISC-V處理器可以正確執行由開源碼的gcc編譯器所編譯出來的程式碼。

關鍵字

處理器 ； 系統單晶片 ； 快取 ； 指令集架構 ； 精簡指令集

並列摘要

The purpose of this research is to design and implement a system-on-chip (SoC) based on the RISC-V instruction set architecture (ISA). RISC-V is an open source ISA based on the Reduced Instruction Set Computing (RISC) principle. Compared to most RISC ISAs, the RISC-V ISA is freely available for any purposes. Allowing anyone to design, manufacture and sell RISC-V chips and software.
In recent years, RISC-V has risen rapidly due to the booming development of the Internet of Things (IoT) and the licensing and patents of the commercial RISC ISA. In response to the fragmentation of IoT scenarios, there is a high demand for low power, low cost and customization, which are the features of RISC-V ISA.
Therefore, in this research, we will design and implementation a RISC-V processor that supports RV32IM. After the design and implementation, we will pass the RISC-V official ISA tests and use the standard Dhrystone benchmark to evaluate the performance (DMIPS/MHz) of our purposed RISC-V processor in a full-system simulation environment. In addition, we will also compile the binary file with the open source GNU Compiler Toolchain and verify the correctness of the proposed process SoC running on the Xilinx FPGA, KC705 development platform.

並列關鍵字

RISC-V ； SoC ； Processor ； Cache ； RISC

參考文獻

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[2] Y. Li, Computer Principles and Design in Verilog HDL, 2015.

[3] P. M. Sailer, P. M. Sailer, and D. R. Kaeli, The DLX instruction set architecture handbook, Morgan Kaufmann Publishers Inc., 1996.

[4] Xilinx, MicroBlaze Overview.[Online] Available:https://www.xilinx.com/products/design-tools/microblaze.html

[5] Xilinx, The MicroBlaze Soft Processor: Flexibility and Performance for Cost-Sensitive Embedded Designs v1.0 (WP501), Xilinx White Paper #501, April 13, 2017.