用於電源開關設計中之元件佈置後的電源網路最佳化方法

Post-Placement Power Network Optimization for Power-Gating Design

李雅菁(Ya-Ching Lee)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.01801

摘要

在先進製程中，電晶體開關(sleep transistor)是一個可以有效降低靜態和動態功率消耗的方法。然而，因為電晶體開關的加入，也會衍生出晶片面積增大、繞線空間減少、電源網路的電壓降增加和電路複雜度增加等問題。為了有效地增加電晶體開關使用的效率，我們提出一套方法，可以快速的調整出一個最佳的電晶體電源網路，讓電源網路的電壓降可以符合要求且可以減少電晶體開關和電源網路的使用面積而增加繞線空間。我們使用兩個設計案例去證實所提出來的方法和流程，結果顯示這個方法確實可以快速的調整出一個最佳的電晶體電源網路和計算出電源網路的電壓降(IR drop)，在電源網路的電壓降可以符合要求的前提下使用較少的電晶體電源網路去提升繞線空間。

關鍵字

電源開關 ； 電源網路

並列摘要

Using sleep transistors to implement the power-gating design is an effective method for reducing dynamic and leakage power in advanced process. However, sleep transistors will encourage extra cost in chip area, reduce routing resource, and increase IR drop and design complexity. Although a denser power network can reduce IR drop, it wastes much routing area. In order to utilize this power-gating technology more efficiently, we propose a post-placement sleep transistor power network optimization method. This method can adjust the power network to meet an expected IR drop and consume smaller power network area. Two test cases are used to verify the both proposed method and design flow. Experimental results show that the proposed post-placement design flow can get accurate IR drop quickly. Furthermore, the proposed Power/Ground network adjustment methodology can also reduce 7.6% and 37.13% Power/Ground area in design 1 and design 2, respectively. So the proposed method can release more space for routing.

並列關鍵字

Power Network ； Power-Gating

參考文獻

[2] B. H. Calhoun, F. A. Honore and A. P. Chandrakasan, “A leakage reduction methodology for distributed MTCMOS”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 5, May 2004.

[4] A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden, “Design and analysis of power distribution networks in PowerPCTM microprocessors,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 738-743, Jun 1998.

[5] F. Hamzaoglu and M. R. Stan, “Circuit-level techniques to control gate leakage for sub-100nm CMOS”, in Proceedings of International Symposium on Low Power Electronics and Design, pp. 60-63, August 2002.

[6] J. Kao, A. Chandrakasan and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 409-414, June 1997.

[7] J. Kao, S. Narendra and A. Chandrakasan, “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 495-500, June 1998.