降低除小數頻率合成器的頻外相位雜訊之研究

Research on Reducing Out-of-Band Phase Noise of Fractional-N Frequency Synthesizer

林嘉豪(Jia-Hau Lin)

指導教授 ： 林坤佑

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.02646

摘要

相位雜訊(phase noise)通常被用來評估頻率合成器性能的優劣。它不僅代表著產生訊號純淨的程度，更可預測相鄰通道訊號相互影響的程度。在特定系統架構下，如射頻接收器或光纖時脈數據恢復電路，頻外相位雜訊(out-of-band phase noise)大小會影響系統的靈敏度(sensitivity)或誤碼率(bit error rate, BER)。而頻外相位雜訊由壓控振盪器(voltage-controlled oscillators, VCOs)的相位雜訊或ΔΣ調變器(delta-sigma modulator, DSM)的量化雜訊(quantization noise)主導。因此消除壓控振盪器的相位雜訊及ΔΣ調變器的量化雜訊可以改善頻率合成器在頻外的相位雜訊。在此論文中，將呈現兩種電路，第一個是在壓控振盪器中串聯電阻改善相位雜訊，另一個是利用相位內插器降低ΔΣ調變器的量化雜訊來改善迴路的相位雜訊。
第一個研究電路的架構為互補式電容電感壓控振盪器(Complementary LC-VCOs)。在振盪器的直流路徑上串聯電阻以減少電晶體操作在飽和區的時間，因此可減少閃爍雜訊(flicker noise)的產生，由此可減少相位雜訊，也代表可以減少頻外相位雜訊。壓控振盪器操作在19.15到22.78 GHz，電路架構包括改良互補式電容電感壓控振盪器、三級電流模式邏輯(current mode logic, CML)除頻器與差動轉單端(differential-to-single, D2S)的電路。壓控振盪器的輸出在1 MHz位移頻率的相位雜訊為-98.4 dBc/Hz，輸出功率為-3.8 dBm，壓控振盪器的功率消耗為2.9 mW，緩衝放大器的功率消耗為8 mW。總晶片大小為0.335 mm2，使用的製程為台積電90奈米CMOS。
第二個電路著重於使用相位內插器(phase interpolator)以縮小最小相位跳變(minimum phase jump)的除小數頻率合成器。利用相位內插器將原本壓控振盪器的輸出訊號週期細切成三十二等分，因此最小相位跳變的大小也跟著縮小三十二倍，進而可以減少ΔΣ調變器產生的量化雜訊。此頻率合成器操作在3.64 GHz頻段，電路架構包括互補式電容電感壓控振盪器、兩級電流模式邏輯除頻器、雙重相位內插器(dual-reference interpolator, DI)、雙重相位內插器的控制器(DI controller, DC)、五級二/三除頻器(2/3 divider cell, 23Cell)、ΔΣ調變器(delta-sigma modulator, DSM)、相位頻率偵測器(phase frequency detector, PFD)，電荷泵(charge pump, CP)及二階低通濾波器(2nd low pass filter, 2nd LPF)，參考頻率為26 MHz，迴路頻寬為66.7 kHz。1 MHz位移頻率的相位雜訊為-115.5 dBc/Hz，輸出功率為-3.573 dBm，總功率消耗為54.7 mW，晶片大小為0.43 mm2，使用的製程為台積電180奈米CMOS。

關鍵字

除小數頻率合成器 ； 相位內插器 ； 改良互補式電感電容壓控振盪器 ； 高位移頻率相位雜訊 ； 量化雜訊

並列摘要

Phase noise is an important parameter to evaluate a frequency synthesizer. It not only represents the degree of purity of output signal, but also can be utilized to predict the effect on signal interaction between two neighboring channels. In regard to some specific systems, such as RF receiver and optical clock-data recovery circuits, out-of-band phase noise dominates the sensitivity and bit error rate (BER) of these systems. Out-of-band phase noise is produced by phase noise of voltage-controlled oscillators (VCOs) and quantization noise of delta-sigma modulator (DSM). Therefore, reducing the phase noise of VCOs and the quantization noise of DSM can improve the out-of-band phase noise of a frequency synthesizer. In this thesis, two circuits are discussed. First one is inserting resistors into the dc path of the VCO to improve phase noise. Another one is utilizing the phase interpolator to reduce the quantization noise of DSM and then the phase noise can be improved.
The first circuit is focused on inserting resistors into the path of direct current of the VCO. Thus the period in saturation region is decreased and the production of flicker noise of the transistors is reduced as well. Finally, the out-of-band phase noise of VCOs can be improved. The VCO is operated at 19.15-22.78 GHz. It includes a modified complementary LC-VCO, a 3-stage current mode logic (CML) divider, and a differential-to-single (D2S) circuit. The VCO phase noise at 1-MHz offset frequency is -98.4 dBc/Hz. Its output power is -3.8 dBm. The power consumption of VCO is 2.9 mW, and the power consumption of buffers is 8 mW. The chip size is 0.335 mm2. It is fabricated by TSMC 90-nm CMOS technology.
The second part of this thesis is focused on utilizing phase interpolator (PI) to reduce minimum phase jump, which has a critical effect on quantization noise. One period of input signal of PI is divided equivalently into 32 parts. Therefore, the minimum phase jump has decreased 32 times. Consequently, the quantization noise of DSM can be reduced as well. This circuit is used to implement a 3.65 GHz fractional-N frequency synthesizer and which includes a complementary LC-VCO, a 2-stage CML divider, a dual-reference interpolator (DI), DI controller (DC), a 5-stage 2/3 divider cell (23Cell), a delta-sigma modulator (DSM), a phase frequency detector (PFD), a charge pump (CP), and a 2nd low pass filter (2nd LPF). The reference frequency is 26 MHz and the loop bandwidth is 66.7 kHz. The phase noise at 1-MHz offset frequency is -115.5 dBc/Hz. The output power is -3.57 dBm, and the total dc consumption is 54.7 mW. It is fabricated by TSMC 180-nm CMOS technology, and the chip size is 0.43 mm2.

並列關鍵字

Fractional-N frequency synthesizer ； phase interpolator ； modified complementary LC-VCO ； out-of-band phase noise ； quantization noise

參考文獻

[1] Chun-Huat Heng, and Bang-Sup Song, “A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO,” IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 848-854, June 2003.

[2] Dong-Woo Jee, Yunjae Suh, Byungsub Kim, Hong-June Park, and Jae-Yoon Sim, “A FIR-embedded phase interpolator based noise filtering for wide-bandwidth fraction-N PLL,” IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp. 2795-2804, Nov. 2013.

[3] Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, and Andrea L. Lacaita, “Suppression of flicker noise up-conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz band,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2375-2389, Oct. 2013.

[4] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma modulation in fractional-N frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.

[5] N. Filiol, T. A. D. Riley, C. Plett, and M. A. Copeland, “An agile ISM band frequency synthesizer with built-in GMSK data modulation,” IEEE J. Solid-State Circuits, vol. 33, pp. 998-1008, July 1998.