S/C及K頻段低雜訊放大器與W頻段注入鎖定式倍頻器之研究

Research of S/C and K-band Low Noise Amplifiers and W-band Injection Locked Frequency Multiplier

張育銓(Yu-Chuan Chang)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.10373

摘要

近年來，微波在工程上的應用蓬勃發展，尤其在無線通訊的應用當中扮演了舉足輕重的角色。高速通訊在今日越來越受到矚目，而無論在有線或是無線的通訊系統中，低雜訊放大器及穩定的信號源都很重要。
本論文主要分成兩部分：第一部分為接收器前端電路之低雜訊放大器相關研究。低雜訊放大器在射頻接收前端系統為一重要元件；它將從天線端接收之微弱的射頻訊號放大並導入較少的雜訊。首先，呈現製作於0.15微米砷化鎵製程，應用於SKA天文計畫之低雜訊放大器研製。藉由準確地選擇電路架構，此低雜訊放大器在2.8到5.18兆赫茲系統規格之頻帶內提供足夠增益(27.5 ± 0.5 dB)及雜訊指數(1 ± 0.2 dB)。
除了低頻帶低雜訊放大器，本論文另展示兩個應用於K頻帶之17.7到20.7兆赫茲之低雜訊放大器。第一顆電路採兩級架構，第一級為共源級架構並串接一疊接組態架構。共源級架構相對於疊接組態有較小的雜訊指數，應此常為低雜訊放大器第一級電路架構。第二顆電路採兩級疊接組態架構，並使用雜訊抑制機制，選擇更小尺寸電晶體當放大單元以降低功耗，並於疊接元件之間加上電感來抑制雜訊並提高高頻穩定度。此兩顆電路皆達到頻帶內增益皆大於15 dB，雜訊指數皆小於3 dB。
第二部分是應用於汽車雷達本地振盪源鍊路之六倍頻器研製。倍頻器目前廣泛使用在射頻收發機系統上，主要功用為將輸入訊號的頻率輸出成特定倍數頻率輸出的諧振電路。一般倍頻器之係數通常不超過四倍，超過四倍時，則以串接多級方式實現。一般傳統六倍頻器多使用二乘三或三乘二架構來實現。但一般非線性放大器組態倍頻器其因低頻匹配電路常使面積過大。本篇論文提出六倍頻器電路採用注入鎖定式三倍頻器並雙推出來經緩衝放大器成六倍頻輸出。較已發表的文獻中，達到有效面積縮減。考慮到系統功率預算分配，於六倍頻器後串接一中等功率放大器。此電路採用65nm CMOS 實現，其鎖定範圍在輸入功率為 0 dBm情情況下，達到9.6 % 範圍，整體面積(含pad)為1.19 mm2。

關鍵字

低雜訊放大器 ； 倍頻器 ； 金氧半場效電晶體 ； 微波單晶積體電路

並列摘要

In recent years, the applications of microwave are widely developed in engineer-ing, especially in wireless communication. Today, high-speed communications are the focus, and the low noise amplifiers and stable sources are important in regardless of wire or wireless communication systems.
This thesis is divided into two parts. The first part presents the development of low noise amplifiers for RF frond end. Low noise amplifiers are a vital element in the RF receiver front-end systems. The weak RF signals received from the antenna are amplified and import less noise in low noise amplifier. Firstly, a low noise amplifier using 0.15-μm GaAs pHEMT for SKA application is presented. By properly choosing circuit architecture, the LNA demonstrates sufficient gain, 27.5 ± 0.5 dB, and excellent noise figure, 1 ± 0.2 dB, from 2.8 to 5.12 GHz which is the SKA band-4.
Also, two K-band low noise amplifiers from 17.7 to 20.7 GHz are investigated in this thesis. Both of them are fabricated in TSMC 90 nm CMOS. The topology of the first circuit is a common source stage cascade with a cascode stage. The noise perfor-mance of common source topology is better than cascode topology and it is usually the first stage at low noise amplifier. The second circuit is two-stage cascode amplifier with choosing smaller transistor size in unit amplifier cell to reduce power consump-tion and noise cancelling technique which adds inductor between the cascode compo-nents for suppressing noise and improve the stability at high frequency band. The two amplifiers have more than 15 dB gain and lower than 3-dB noise performance in the target band.
The second part of the thesis is about an injection-locked frequency sextupler us-ing 65-nm CMOS for automotive radar applications. Multiplier is widely used in RF transceiver systems. Usually, the multiplier is not be implemented more than four times. For the multiple greater than four, the cascade topology is more popular. Tradi-tionally sextupler are often achieved by cascade doubler and tripler. However, the non-linear-amplifier-based frequency multiplier is a bit of large because of the low-frequency matching circuits. In this thesis, the injection-locked tripler with push-push topology is used to get the six times input frequency after the buffer stage. For the consideration of system power budget, a medium power amplifier is cascaded at the frequency sextupler. At input power 0 dBm, the locking range of this sextupler is 9.6 % and the area is 0.42 mm2 including pads.

並列關鍵字

low noise amplifier ； Multiplier ； MMIC ； pHEMT ； CMOS ； SKA

參考文獻

[3] H.J. Ng, R. Feger, and A. Stelzer, "A fully-integrated 77-GHz UWB pseu-do-random noise radar transceiver with a programmable sequence generator in SiGe technology," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, no.8, pp.2444-2455, Aug. 2014.

[4] Jri Lee, Yi-An Li, Meng-Hsiung Hung, and Shih-Jou Huang, "A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology," IEEE Journal of Solid-State Circuits, vol.45, no.12, pp.2746-2756, Dec. 2010.

[7] L. Belostotski, and J.W. Haslett, “Wide band room temperature 0.35-dB noise figure LNA in 90-nm bulk CMOS,” in IEEE Radio Wireless Symposium. Dig., Jan., 2007.

[8] N. Shiramizu, T. Masuda, M. Tanabe, and K. Washio, “A 3-10 GHz bandwidth low-noise and low-power amplifier for full-band UWB communications in 0.25-µm SiGe BiCMOS technology,” IEEE Radio Frequency Integrated Circuits Symposium. Dig., Jun., 2005.

[10] P.-L. Hai, K. Shah, and J. Singh, “A fully-on-chip wideband low noise amplifier for radio telescope applications,” in IEEE International Symposium on Circuits and Systems, May, 2009.