多重編碼率階層式低密度奇偶校正碼解碼器之疊代控制演算法

An Iteration Control Algorithm for Multi-Rate Layered LDPC Decoder

劉建邦(Jian-Bang Liu)

指導教授 ： 顧孟愷

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.02899

摘要

在LDPC解碼器中，疊代次數的控制是一個重要的議題，因為疊代次數控制得當可以增加解碼的速率以及減少功率消耗。在這篇論文中，我們提出了一個適用於多重編碼率階層式LDPC解碼器的疊代控制演算法。這個演算法可以準確地偵測成功解碼並提早結束解碼程序而不會有位元錯誤率的損失。而對於無法成功解碼的情況，我們提出了一個低計算成本的度量標準用以提早檢測出無法成功解碼之字碼。而模擬結果顯示出我們的演算法可以有效的減少解碼所需的平均疊代次數，而僅有些微的位元錯誤率損失。實作上，部份並行的策略使得我們的演算法可以輕易的與多重編碼率階層式LDPC解碼器作整合。FPGA的實作結果顯示出演算法只增加了1.0％的硬體成本在一個32並行程序的多重編碼率階層式LDPC解碼器上。

關鍵字

低密度奇偶校驗碼 ； 解碼器 ； 疊代次數控制

並列摘要

Iteration control is an important issue for the iterative decoding of LDPC codes since it can tremendously increase the decoding throughput or reduce the power consumption. In this thesis, we proposed an iteration control algorithm for the multi-rate layered decoder. Our iteration control algorithm introduces no bit error rate (BER) degradation in successful decoding detection. For unsuccessful decoding, we proposed a low computation complexity decision metric for early detect undecodable blocks. Simulation results show that our proposed algorithm can significantly reduce average number of decoding iterations while maintains the BER performance. Partially parallel characteristic of proposed algorithm makes it easily integrated into multi-rate layered LDPC decoder. The FPGA implementation results show that our architecture only add 1.0% hardware cost to a 32-thread multi-rate layered decoder.

並列關鍵字

LDPC ； decoder ； iteration control

參考文獻

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