全數位式鎖相迴路之設計與實作

Design and Implementation of an All Digital Phase Lock Loop

蔡勝中(Sheng-Chung Tsai)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.02192

摘要

無資料

關鍵字

全數位式 ； 鎖相迴路

並列摘要

ABSTRACT

In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. A 16-bit digitally controlled CMOS oscillator uses a 4-stage ring of a modified differential delay cell. The DCO uses the even-stage skew dual-delay path scheme [11], which enables higher operating frequency. The frequency search and the phase tracking are major blocks in a control unit. We use a high sensitivity phase tracking and frequency search algorithm, which consists two D-type flip flop and some logical circuits.
In our proposed ADPLL, we implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in the TSMC 0.18μm 1P6M technology. The supply voltage is 1.8V. The simulation results show that when DCO operates at 2.4GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 30 reference clock cycles (algorithm). The lock-in range is 2.07GHz to 2.56GHz. The power consumption is 106.1mW at 2.4GHz.

並列關鍵字

ADPLL ； DCO

參考文獻

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[3] J.-S. Chiang and K.-Y. Chen, “The design of an all-digital phase- locked loop with small DCO hardware and fast phase lock,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 7, pp. 945-950, Jul 1999.

[6] C.-C. Chung and C.-Y. Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol.38, no. 2, pp. 347-351, Feb 2003.

[8] S. M. Rezaul Hasan, “A 5 GHz CMOS Digitally Controlled Oscillator with 3 GHz Tuning Range for PLL applications,” IEEE International Conference on Electronics, Circuits and Systems, vol 1, pp. 208-211, Dec 2003

[10] Guang-Kaii Dehng, June-Ming Hsu, Ching-Yuan Yang, and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1128-1136, Aug. 2000.