針對微小延遲缺陷選取緊密的測試向量

為了在先進的奈米製程技術下確保產品的品質，針對微小延遲缺陷進行測試已經成為必要的課題。在現有的商用測試軟體工具中，針對微小延遲缺陷的自動測試向量產生技術仍然存在著過長的測試向量產生時間以及過量的測試向量等問題。因此，本論文提出了一套選擇測試向量的演算法，從商用軟體針對延遲缺陷所產生出來的測試向量中選取一個可以有效測試微小延遲缺陷的測試向量集。本論文所提出的演算法有效的對電路結構上延遲缺陷所傳遞路徑的上下限進行分析，以迅速估算在一組測試向量下微小延遲缺陷所被傳遞的路徑長度。如此，此演算法在選取測試向量的過程中可以有效的降低所需要花費的時間。由於大部分在電路中的延遲缺陷都很容易被偵測到，所以本論文在選擇測試向量的過程中，只建立一個局部的錯誤對應字典，而不是一個完整的字典，用來將目標鎖定在那些較難偵測到的延遲缺陷上。根據實驗結果顯示，本論文提出的演算法選出的測試向量和商用軟體針對微小延遲缺陷所產生的測試向量有著很接近的測試向量品質，並且利用此演算法所選擇出的測試向量集比商用軟體所產生出來的測試向量集小了百分之三十二。因此，利用本論文所提出的演算法，針對微小延遲缺陷進行測試所需的花費將不再如以往昂貴。

關鍵字

選取測試向量；微小延遲缺陷

並列摘要

Testing for small delay defect (SDD) is necessary for ensuring product quality in modern nanometer technologies. Existing commercial tools such as transition fault Automatic Test Pattern Generation (ATPG) tools and timing-aware ATPG tools are either inefficient in detecting SDD or suffering from large CPU time and pattern count. Therefore, this thesis proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so the CPU time can be reduced in pattern selection process. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results show that, with very similar quality, the selected test set is 32% smaller than that of timing-aware ATPG. With the proposed selection algorithm, SDD test sets are no longer too expensive to apply.

並列關鍵字

Pattern Selection ； Small Delay Defect

參考文獻

[Ahmed 06] N. Ahmed, M. Tehranipoor, V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects”, . In Proc. of IEEE Design Automation Conf., pages 320–325, 2006

[Goel 09] S. K. Goel, N. Devta-Prasanna, and R. P. Turakhia, “Effective and Efficient Test Pattern Generation for Small Delay Defect,” Proc. IEEE VLSI Test Symp., pp. 111–116, 2009

[Goel 10] S. K. Goel, K. Chakrabarty, M. Yilmaz, K. Peng, and M. Tehranipoor, “Circuit Topology-Based Test Pattern Generation for Small Delay Defects,” Proc. IEEE Asian Test Symp., pp. 307–312, 2010.

[Gupta 04] P. Gupta and M.S. Hsiao, “ALAPTF: A New Transition Fault Model and the ATPG Algorithm,” Proc. IEEE Int’l Test Conf., pp. 1053-1060, 2004

[ITRS 2007] International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net/Links/2007ITRS/Home2007.htm.

國際替代計量

針對微小延遲缺陷選取緊密的測試向量

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