轉態延遲障礙之決定型測試向量產生器設計

Efficient Deterministic Pattern Generator for Transition Faults Testing

吳書緯(Shu-Wei Wu)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2010年)

https://doi.org/10.6840/cycu201000691

摘要

在本篇論文中，我們提出一種針對轉態延遲障礙的決定型測試向量產生器(Deterministic Test Pattern Generator, DTPG)，此DTPG單純由線性迴授位移暫存器(Linear Feedback Shift Register, LFSR)以及相位平移器(Phase Shifter, PS)所組合而成。利用此DTPG可在50K的測試長度內達成原本1000K測試長度才能達到的測試涵蓋率，以及少量額外電路面積(Area Overhead)的目標。

關鍵字

相位平移器 ； 決定型測試向量產生器 ； 轉態延遲障礙

並列摘要

In this thesis, we propose a method to design a deterministic test pattern generator (DTPG) for transition delay fault, by using a linear feedback shift register (LFSR) and phase shifter. This DTPG can achieve the fault coverage in 50K test length which the original need 1000K test length, and only need few hardware overhead.

並列關鍵字

transition faults ； deterministic pattern generator ； phase shifter

參考文獻

[3] 湯燕飛 (2009)。決定型測試向量產生器之有效設計。(碩士論文，中原大學，2009)。全國博碩士論文資訊網，097CYCU5428048。

[4] V. Gherman, H.-J. Wunderlich, J. Schloeffel and M. Garbers, “Deterministic Logic BIST for Transition Fault Testing," European Test Sym., pp.123-130, May 2006.

參考文獻

[1] A. Jutman, I. Aleksejev, J. Raik and R. Ubar, “Reseeding using Compaction of Pre-Generated LFSR Sub-Sequences,” IEEE International Conference on Electronics, Circuits and Systems, pp.1290 – 1295, 2008.

[2] J. Rajski, N. Tamarapalli and J. Tyszer, “Automated synthesis of phase shifters for built-in self-test applications,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Issue 10, pp.1175-1188, Oct. 2000.