決定型測試向量產生器之有效設計

An Efficient Design of Deterministic Test Pattern Generator

湯燕飛(Yan-Fei Tang)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2009年)

https://doi.org/10.6840/cycu200901166

摘要

內建自我測試(Build-In Self-Test, BIST)技術係屬於系統單晶片(System-on-Chip, SoC)測試中一種非常有效的方法。在內建自我測試技術中，最重要的一件事是測試向量產生器(Test Pattern Generator, TPG)的設計，常用的方法是假型隨機向量產生器(Pseudo-Random Pattern Generator, PRPG)，例如線性迴授位移暫存器(Linear Feedback Shift Register, LFSR)。本論文提出一個有效的方法，設計由線性迴授位移暫存器與Phase Shifter組成的決定型測試向量產生器(Deterministic Test Pattern Generator, DTPG)，達成一些目標，包括高向量命中率(Pattern Hit Rate)、障礙涵蓋率(Fault Coverage)、低測試時脈時間(Test Clock Time)與少量額外電路面積(Area Overhead)。

關鍵字

相位平移器 ； 線性迴授位移暫存器 ； 決定型測試向量產生器

並列摘要

Build-in self-test (BIST) is very efficient for system-on-chip (SoC) testing. In BIST design, test pattern generators (TPG) are the most important architecture. Pseudo-random pattern generator, e.g. linear feedback shift register (LFSR), is a common TPG. In this thesis, we propose an efficient method to design a deterministic TPG by using a LFSR and a phase shifter. The deterministic TPG can achieve some objectives like high pattern hit rate, high test coverage, short test clock time, and low area overhead.

並列關鍵字

LFSR ； Deterministic Test Pattern Generator ； Phase Sifter

參考文獻

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[1] J. Rajski, N. Tamarapalli and J. Tyszer, “Automated synthesis of phase shifters for built-in self-test applications,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Issue 10, pp.1175-1188, Oct. 2000.