Designing Circuits for Low-Power Testing of Transition Delay Faults

Integrated circuits usually consume much more power during test mode than in normal operation. This may hurts circuits or causes invalid test results, making lowpower testing become very important nowadays. In this paper, we propose a new scan flip-flop for a novel low-power multiple scan test architecture for testing transition delay faults (TDF). We also design a new controller to make the multiple scan chains be shifted in segment by segment and only one segment for each scan chain is launched and captured for low-power testing. Both launch-off-shift (LOS) and launch-off-capture (LOC) testing for TDF can be performed in our architecture. The proposed design increases little area overhead and requires very few additional inputs to achieve lowpower testing for circuits under test.

關鍵字

launch-off-shift ； launch-off-capture ； transition delay fault ； multiple scan chains

並列摘要

積體電路在測試模式時，經常比在平常使用模式，消耗更多的功率，如此會損壞電路，或是造成錯誤測試結果，低功率測試因此成為非常重要的課題。在此研究中，我們為一特別的低功率多掃瞄串測試架構，提出一個新型的掃瞄正反器設計，使能測試轉態延遲障礙；我們也設計一個新型的控制器，用以驅使多掃瞄串能逐段地進行位移，同時也只讓掃瞄串中的一個掃瞄段，單獨進行投值及抓值動作，達成低功率測試的目標。此控制器可以應用於位移時投值以及在抓取時投值兩種測試方式之進行。我們提出的新型掃瞄正反器及控制器，為待測電路只增加很少的電路面積，也需要很少的額外輸入信號，即可達成低功率的測試效果。

並列關鍵字

位移時投值；抓取時投值；轉態延遲障礙；多掃瞄串

國際替代計量

Designing Circuits for Low-Power Testing of Transition Delay Faults

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