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  • 學位論文

利用原子層沉積技術成長高介電常數介電層於二硫化鎢及高定向熱解石墨之成核工程

Nucleation Engineering for Atomic Layer Deposition of High-K Gate Dielectric on WS2 and HOPG

指導教授 : 陳敏璋

摘要


在本論文的第一部分,我們製作並研究了上閘極二硫化鎢(WS2)電晶體。採用低溫NanoFog ALD作為成核層及傳統加熱式原子層沉積(Atomic Layer Deposition, ALD)作為主層制備閘極介電層。汲極電流對閘極電壓(Id-Vg)的特性曲線顯示二硫化鎢電晶體的開關比高達106,次臨界擺幅低至83 mV/dec,且閘極漏電流為雜訊等級。 論文的第二部分利用原子層播種(Atomic Layer Seeding, ALS)技術研究了氧化鋯(ZrO2)在高定向熱解石墨(highly oriented pyrolytic graphite, HOPG)上的成核行為,並調查了溫度和前驅體/反應物劑量對反應的影響。在良好的製程條件下,可實現表面粗糙度(Ra)低至0.331nm的均勻覆蓋。進一步的拉曼光譜分析表明,ALS技術並沒有對HOPG基板造成結構損傷。 在本論文的最後一部分,通過20次ALD循環的低功率遠程電漿增強原子層播種(remote plasma atomic layer seeding, RPALS)技術,可以在HOPG上均勻覆蓋氮化矽(SiNx)薄膜。20次ALD循環的RPALS 氮化矽加上40次循環的ALD 氧化鉿(HfO2)的總等效氧化層厚度(equivalent oxide thickness, EOT)為2.21nm。

並列摘要


In the first part of this thesis, top-gated WS2-field effect transistors were fabricated and investigated. The gate dielectric was prepared via the low temperature NanoFog ALD (NF-ALD) method for the nucleation layer and conventional thermal atomic layer deposition (ALD) for the main layer. The drain current versus gate voltage (Id-Vg) transfer characteristics reveals a high on/off ratio of 106 and a low subthreshold slope of 83 mV/dec, along with noise-level gate leakage current. The second part of this thesis reported the nucleation behavior of zirconium oxide (ZrO2) on highly oriented pyrolytic graphite (HOPG) via the atomic layer seeding (ALS) technique. The effects of temperature and precursor/reactant dose were investigated. Under the optimized condition, uniform coverage with surface roughness (Ra) as low as 0.331 nm can be achieved. Further examination Raman spectroscopy shows that the deposition process does not cause structural damage to the HOPG substrate. In the last part of this thesis, uniform coverage of silicon nitride on HOPG was accomplished by preparing 20 ALD cycles of the low power remote plasma atomic layer seeding (RPALS). The total equivalent oxide thickness (EOT) of 20-cycle RPALS SiNx and 40-cycle ALD HfO2 was 2.21 nm.

參考文獻


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