基於數位時間轉換器之開迴路小數除頻器的設計與實現

Design and Implementation of an Open-Loop Fractional Output Divider Based on Digital-to-Time Converter

洪宇廷(Yu-Ting Hung)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202000778

摘要

近年來，由於積體電路的快速演進，在高科技電子產品當中常常會包含許多系統晶片。而一個系統晶片往往又由各種不同的子晶片或是記憶體所組成。這些子晶片以及記憶體通常需要各種不同頻率的輸入時脈。在傳統的系統晶片中，每一種不同的時脈都需要一個鎖相迴路配合以便提供穩定而且準確的頻率。然而，大量使用鎖相迴路於一個系統晶片中不但占據大量面積而且消耗巨大功率，如果能使用多個小數輸出除頻器搭配單一鎖相迴路即可解決以上所提到的問題。
本作品為一個以數位對時間轉換器為基底之開迴路小數除頻器，其輸出頻率範圍為0.625-200百萬赫茲。此作品的應用為提供時脈給單一系統晶片內，操作於不同頻率的子電路，以維持正常操作。以單一時脈產生器搭配數個本作品之除頻器，可以節省多個不同頻率時脈產生器的面積以及功率消耗。本作品以台積電 90奈米製程實現。量測結果顯示在不同的除數下，本作品能正確地操作。輸出訊號量測得到之均方根時基誤差(RMS Jitter)在校正電路完成校正之後約為120飛秒，而此作品在1伏特的操作電壓下，最大功率消耗為1.45毫瓦。除此之外，此作品還可以同時支援展頻的功能。

關鍵字

數位對時間轉換器 ； 除頻器 ； 展頻

並列摘要

A system-on-chip (SoC) usually consists of multiple subsystems. These subsystems operate at different clock frequencies. In conventional solution, each subsystem needs a phase-locked loop (PLL) for generating stable and accurate frequency. However, using multiple PLLs in a system consume large chip area and high power consumption. An alternative method which uses only one PLL and several fractional output dividers can solve the problem mentioned above.
This thesis presents “a 0.625~200 MHz DTC-based open loop fractional output divider”. This work supports wide output frequency range. This chip is fabricated in TSMC 90-nm CMOS technology. The measurement results show that the proposed fractional output divider operates properly both in the integer mode and fractional mode. The measured RMS Jitter is 120 fs when the calibration circuit is finished. The overall power consumption of this work is 1.45 mW under 1-V supply voltage. Furthermore, this work can support the required clocking function for spread spectrum.

並列關鍵字

Digital-to-Time Converter ； Frequency Divider ； Spread Spectrum

參考文獻

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